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José Luis Neves: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]
Publications of Author
- Yehea I. Ismail, Eby G. Friedman, José Luis Neves
Figures of Merit to Characterize the Importance of On-Chip Inductance. [Citation Graph (0, 0)][DBLP]
DAC, 1998, pp:560-565 [Conf] - Yehea I. Ismail, Eby G. Friedman, José Luis Neves
Equivalent Elmore Delay for RLC Trees. [Citation Graph (0, 0)][DBLP]
DAC, 1999, pp:715-720 [Conf] - José Luis Neves, Eby G. Friedman
Optimal Clock Skew Scheduling Tolerant to Process Variations. [Citation Graph (0, 0)][DBLP]
DAC, 1996, pp:623-628 [Conf] - Yehea I. Ismail, Eby G. Friedman, José Luis Neves
Dynamic and Short-Circuit Power of CMOS Gates Driving Lossless Transmission Lines. [Citation Graph (0, 0)][DBLP]
Great Lakes Symposium on VLSI, 1998, pp:39-44 [Conf] - Yehea I. Ismail, Eby G. Friedman, José Luis Neves
Inductance Effects in RLC Trees. [Citation Graph (0, 0)][DBLP]
Great Lakes Symposium on VLSI, 1999, pp:56-59 [Conf] - Yehea I. Ismail, Eby G. Friedman, José Luis Neves
Repeater insertion in tree structured inductive interconnect. [Citation Graph (0, 0)][DBLP]
ICCAD, 1999, pp:420-424 [Conf] - José Luis Neves, Stephen T. Quay
Buffer Library Selection. [Citation Graph (0, 0)][DBLP]
ICCD, 2000, pp:221-226 [Conf] - José Luis Neves, Eby G. Friedman
Circuit Synthesis of Clock Distribution Networks Based on Non-Zero Clock Skew. [Citation Graph (0, 0)][DBLP]
ISCAS, 1994, pp:175-178 [Conf] - José Luis Neves, Eby G. Friedman
Minimizing Power Dissipation in Non-Zero Skew-Based Clock Distribution Networks. [Citation Graph (0, 0)][DBLP]
ISCAS, 1995, pp:1576-1579 [Conf] - Charles J. Alpert, Gopal Gandham, Jiang Hu, José Luis Neves, Stephen T. Quay, Sachin S. Sapatnekar
Steiner tree optimization for buffers. Blockages and bays. [Citation Graph (0, 0)][DBLP]
ISCAS (5), 2001, pp:399-402 [Conf] - Yehea I. Ismail, Eby G. Friedman, José Luis Neves
Signal waveform characterization in RLC trees. [Citation Graph (0, 0)][DBLP]
ISCAS (6), 1999, pp:190-193 [Conf] - Yehea I. Ismail, Eby G. Friedman, José Luis Neves
Power dissipated by CMOS gates driving lossless transmission lines. [Citation Graph (0, 0)][DBLP]
ISLPED, 1998, pp:139-142 [Conf] - Yehea I. Ismail, Eby G. Friedman, José Luis Neves
Inductance Effects in RLC Trees. [Citation Graph (0, 0)][DBLP]
Journal of Circuits, Systems, and Computers, 2002, v:11, n:3, pp:305-0 [Journal] - Charles J. Alpert, Gopal Gandham, Jiang Hu, José Luis Neves, Stephen T. Quay, Sachin S. Sapatnekar
Steiner tree optimization for buffers, blockages, and bays. [Citation Graph (0, 0)][DBLP]
IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:4, pp:556-562 [Journal] - Yehea I. Ismail, Eby G. Friedman, José Luis Neves
Equivalent Elmore delay for RLC trees. [Citation Graph (0, 0)][DBLP]
IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:1, pp:83-97 [Journal] - José Luis Neves, Eby G. Friedman
Design methodology for synthesizing clock distribution networks exploiting nonzero localized clock skew. [Citation Graph (0, 0)][DBLP]
IEEE Trans. VLSI Syst., 1996, v:4, n:2, pp:286-291 [Journal] - Yehea I. Ismail, Eby G. Friedman, José Luis Neves
Figures of merit to characterize the importance of on-chip inductance. [Citation Graph (0, 0)][DBLP]
IEEE Trans. VLSI Syst., 1999, v:7, n:4, pp:442-449 [Journal]
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