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Dinesh Somasekhar: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Mark C. Johnson, Dinesh Somasekhar, Kaushik Roy
    Leakage Control with Efficient Use of Transistor Stacks in Single Threshold CMOS. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:442-445 [Conf]
  2. Dinesh Somasekhar, Seung Hoon Choi, Kaushik Roy, Yibin Ye, Vivek De
    Dynamic noise analysis in precharge-evaluate circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:243- [Conf]
  3. Hendrawan Soeleman, Dinesh Somasekhar, Kaushik Roy
    IDD Waveforms Analysis for Testing of Domino and Low Voltage Static CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1998, pp:243-248 [Conf]
  4. Khurram Muhammad, Dinesh Somasekhar, Kaushik Roy
    Switching Characteristics of Generalized Array Multiplier Architectures and their Applications to Low Power Design. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:230-235 [Conf]
  5. Alexandre Solomatnikov, Kaushik Roy, Cheng-Kok Koh, Dinesh Somasekhar
    Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit Family. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:241-246 [Conf]
  6. Dinesh Somasekhar, Kaushik Roy
    LVDCSL: low voltage differential current switch logic, a robust low power DCSL family. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1997, pp:18-23 [Conf]
  7. Patrick Ndai, Shih-Lien Lu, Dinesh Somasekhar, Kaushik Roy
    Fine-Grained Redundancy in Adders. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:317-321 [Conf]
  8. Dinesh Somasekhar, V. Visvanathan
    A 230MHz Half Bit Level Pipelined Multiplier Using True Single Phase Clocking. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:347-350 [Conf]
  9. Mark C. Johnson, Dinesh Somasekhar, Kaushik Roy
    Models and algorithms for bounds on leakage in CMOS circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:6, pp:714-725 [Journal]
  10. Yibin Ye, Muhammad M. Khellah, Dinesh Somasekhar, Vivek De
    Evaluation of differential vs. single-ended sensing and asymmetric cells in 90 nm logic technology for on-chip caches. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  11. Dinesh Somasekhar, V. Visvanathan
    A 230-MHz half-bit level pipelined multiplier using true single-phase clocking. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:4, pp:415-422 [Journal]
  12. Dinesh Somasekhar, Kaushik Roy
    LVDCSL: a high fan-in, high-performance, low-voltage differential current switch logic family. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:573-577 [Journal]
  13. Mark C. Johnson, Dinesh Somasekhar, Lih-Yih Chiou, Kaushik Roy
    Leakage control with efficient use of transistor stacks in single threshold CMOS. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:1, pp:1-5 [Journal]
  14. Alexandre Solomatnikov, Dinesh Somasekhar, Naran Sirisantana, Kaushik Roy
    Skewed CMOS: noise-tolerant high-performance low-power static circuit family. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:4, pp:469-476 [Journal]

  15. Reducing cache power with low-cost, multi-bit error-correcting codes. [Citation Graph (, )][DBLP]


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