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Seong-Ook Jung: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang
    Low-swing clock domino logic incorporating dual supply and dual threshold voltages. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:467-472 [Conf]
  2. Ki-Wook Kim, Seong-Ook Jung, Prashant Saxena, C. L. Liu, Sung-Mo Kang
    Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:732-737 [Conf]
  3. Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang
    Dual Threshold Voltage Domino Logic Synthesis for High Performance with Noise and Power Constrain. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:260-267 [Conf]
  4. Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang
    Transistor sizing for reliable domino logic design in dual threshold voltage technologies. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:133-138 [Conf]
  5. Seung-Moon Yoo, Seong-Ook Jung, Sung-Mo Kang
    2-level LFSR scheme with asynchronous test pattern transfer for low cost and high efficiency build-in-self-test. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:93-96 [Conf]
  6. Ki-Wook Kim, Seong-Ook Jung, Sung-Mo Kang
    Coupling-aware minimum delay optimization for domino logic circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:371-374 [Conf]
  7. Seung-Moon Yoo, Chulwoo Kim, Seong-Ook Jung, Kwang-Hyun Baek, Sung-Mo Kang
    New current-mode sense amplifiers for high density DRAM and PIM architectures. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:938-941 [Conf]
  8. Seong-Ook Jung, Seung-Moon Yoo, Ki-Wook Kim, Sung-Mo Kang
    Skew-tolerant high-speed (STHS) domino logic. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:154-157 [Conf]
  9. Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang
    Noise constrained power optimization for dual VT domino logic. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:158-161 [Conf]
  10. Seung-Moon Yoo, Seong-Ook Jung, Sung-Mo Kang
    Low cost and high efficiency BIST scheme with 2-level LFSR and ATPT. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:1-4 [Conf]
  11. Ge Yang, Seong-Ook Jung, Kwang-Hyun Baek, Soo Hwan Kim, Suki Kim, Sung-Mo Kang
    A low-power 1.85 GHz 32-bit carry lookahead adder using Dual Path All-N-Logic. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:781-784 [Conf]
  12. Ki-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L. Liu, Sung-Mo Kang
    Noise-aware power optimization for on-chip interconnect. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2000, pp:108-113 [Conf]
  13. Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang
    Optimal Timing for Skew-Tolerant High-Speed Domino Logic. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2002, pp:41-46 [Conf]
  14. Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang
    Timing constraints for domino logic gates with timing-dependent keepers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:1, pp:96-103 [Journal]
  15. Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Sung-Mo Kang
    Minimum delay optimization for domino circuits - a coupling-aware approach. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2003, v:8, n:2, pp:202-213 [Journal]
  16. Ge Yang, Seong-Ook Jung, Kwang-Hyun Baek, Soo Hwan Kim, Suki Kim, Sung-Mo Kang
    A 32-bit carry lookahead adder using dual-path all-N logic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:8, pp:992-996 [Journal]
  17. Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang
    Noise constrained transistor sizing and power optimization for dual Vst domino logic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:5, pp:532-541 [Journal]
  18. Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Prashant Saxena, C. L. Liu, S.-M. S. Kang
    Coupling delay optimization by temporal decorrelation using dual threshold voltage technique. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:5, pp:879-887 [Journal]
  19. Ki-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L. Liu, Sung-Mo Kang
    Noise-aware interconnect power optimization in domino logic synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:1, pp:79-89 [Journal]

  20. Slope interconnect effort: gate-interconnect interdependentdelay model for CMOS logic gates. [Citation Graph (, )][DBLP]


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