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Spyros Tragoudas: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Dimitrios Kagaris, Spyros Tragoudas
    Partial Scan with Retiming. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:249-254 [Conf]
  2. M. M. Vaseekar Kumar, Spyros Tragoudas, Sreejit Chakravarty, Rathish Jayabharathi
    Implicit and Exact Path Delay Fault Grading in Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:990-995 [Conf]
  3. Saravanan Padmanaban, Spyros Tragoudas
    Exact Grading of Multiple Path Delay Faults. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:84-88 [Conf]
  4. Saravanan Padmanaban, Spyros Tragoudas
    Non-Enumerative Path Delay Fault Diagnosis . [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10322-10327 [Conf]
  5. Saravanan Padmanaban, Spyros Tragoudas
    Using BDDs and ZBDDs for Efficient Identification of Testable Path Delay Faults. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:50-55 [Conf]
  6. Spyros Tragoudas, Maria K. Michael
    ATPG Tools for Delay Faults at the Functional Level. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:631-0 [Conf]
  7. Dimitrios Kagaris, Spyros Tragoudas
    LFSR/SR Pseudo-Exhaustive TPG in Fewer Test Cycles. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:130-138 [Conf]
  8. Dimitrios Kagaris, Spyros Tragoudas, Amitava Majumdar
    On-Chip Test Embedding for Multi-Weighted Random LFSRs. [Citation Graph (0, 0)][DBLP]
    DFT, 1998, pp:135-0 [Conf]
  9. Spyros Tragoudas, N. Denny
    Testing for Path Delay Faults Using Test Points. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:86-94 [Conf]
  10. Kyriakos Christou, Maria K. Michael, Spyros Tragoudas
    Implicit Critical PDF Test Generation with Maximal Test Efficiency. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:50-58 [Conf]
  11. Sandeep Dechu, Manoj Kumar Goparaju, Spyros Tragoudas
    A Metric of Tolerance for the Manufacturing Defects of Threshold Logic Gates. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:318-326 [Conf]
  12. Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis
    Accelerating DSP Applications on a Mixed Granularity Platform with a New Reconfigurable Coarse-Grain Data-Path. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:275-276 [Conf]
  13. Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis
    A novel coarse-grain reconfigurable data-path for accelerating DSP kernels. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:252- [Conf]
  14. Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis
    Mapping DSP Applications to a High-Performance Reconfigurable Coarse-Grain Data-Path. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:868-873 [Conf]
  15. M. M. Vaseekar Kumar, Saravanan Padmanaban, Spyros Tragoudas
    Low power ATPG for path delay faults. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:389-392 [Conf]
  16. M. M. Vaseekar Kumar, Spyros Tragoudas
    Low power test generation for path delay faults using stability functions. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:8-12 [Conf]
  17. Dimitrios Karayiannis, Spyros Tragoudas
    Uniform area timing-driven circuit implementation. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1995, pp:2-7 [Conf]
  18. Stelios Neophytou, Maria K. Michael, Spyros Tragoudas
    Test set enhancement for quality transition faults using function-based methods. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:182-187 [Conf]
  19. Spyros Tragoudas, Maria K. Michael
    Functional ATPG for Delay Faults. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:16-19 [Conf]
  20. Dimitrios Kagaris, Spyros Tragoudas, Grammati E. Pantziou, Christos D. Zaroliagis
    Quickest paths: parallelization and dynamization . [Citation Graph (0, 0)][DBLP]
    HICSS (2), 1995, pp:39-40 [Conf]
  21. Dimitrios Kagaris, Spyros Tragoudas
    Maximum independent sets on transitive graphs and their applications in testing and CAD. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:736-740 [Conf]
  22. Dimitrios Kagaris, Fillia Makedon, Spyros Tragoudas
    On Minimizing Hardware Overhead for Pseudoexhaustive Circuit Testability. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:358-364 [Conf]
  23. Dimitrios Kagaris, Spyros Tragoudas
    Pseudoexhaustive TPG with a Provably Low Number of LFSR Seeds. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:42-47 [Conf]
  24. Dimitrios Kagaris, Spyros Tragoudas
    A Class of Good Characteristics Polynomials for LFSR Test Pattern Generators. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:292-295 [Conf]
  25. Dimitrios Kagaris, Spyros Tragoudas
    A multiseed counter TPG with performance guarantee. [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:34-39 [Conf]
  26. Dimitrios Kagaris, Spyros Tragoudas, Dinesh Bhatia
    Pseudoexhaustive BIST for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:523-527 [Conf]
  27. Dimitrios Kagaris, Spyros Tragoudas, Dimitrios Karayiannis
    Nonenumerative Path Delay Fault Coverage Estimation with Optimal Algorithms. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:366-371 [Conf]
  28. D. Kuguris, Spyros Tragoudas
    FPGA Module Minimization. [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:566-571 [Conf]
  29. M. M. Vaseekar Kumar, Spyros Tragoudas
    Quality Transition Fault Tests Suitable for Small Delay Defects. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:468-470 [Conf]
  30. Maria K. Michael, Kyriakos Christou, Spyros Tragoudas
    Towards finding path delay fault tests with high test efficiency using ZBDDs. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:464-467 [Conf]
  31. Dimitri Kagaris, Spyros Tragoudas
    Using a WLFSR to Embed Test Pattern Pairs in Minimum Time. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2001, pp:75-79 [Conf]
  32. Dimitri Kagaris, Spyros Tragoudas
    InTeRail: Using Existing and Extra Interconnects to Test Core-Based SOCs. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2003, pp:219-224 [Conf]
  33. Stelios Neophytou, Maria K. Michael, Spyros Tragoudas
    Efficient Deterministic Test Generation for BIST Schemes with LFSR Reseeding. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2006, pp:43-50 [Conf]
  34. Antonios Symvonis, Spyros Tragoudas
    Searching a Solid Pseudo 3-Sided Orthoconvex Grid. [Citation Graph (0, 0)][DBLP]
    ISAAC, 1992, pp:188-197 [Conf]
  35. Dimitrios Kagaris, Spyros Tragoudas
    Embedded cores using built-in mechanisms. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:23-26 [Conf]
  36. Arkan Abdulrahman, Spyros Tragoudas
    Power-Aware Test Pattern Generation for Improved Concurrency at the Core Level. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:300-305 [Conf]
  37. Rajsekhar Adapa, Spyros Tragoudas, Maria K. Michael
    Evaluation of Collapsing Methods for Fault Diagnosis. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:439-444 [Conf]
  38. Jayant Deodhar, Spyros Tragoudas
    Color Counting and its Application to Path Delay Fault Coverage. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:378-383 [Conf]
  39. Themistoklis Haniotakis, Spyros Tragoudas, G. Pani
    Reduced Test Application Time Based on Reachability Analysis. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:232-237 [Conf]
  40. Edward Flanigan, Themistoklis Haniotakis, Spyros Tragoudas
    An Improved Method for Identifying Linear Dependencies in Path Delay Faults. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:457-462 [Conf]
  41. M. Moiz Khan, Spyros Tragoudas
    Rewiring for Watermarking Digital Circuits. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:143-148 [Conf]
  42. Maria K. Michael, Stelios Neophytou, Spyros Tragoudas
    Functions for Quality Transition Fault Tests. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:327-332 [Conf]
  43. Maria K. Michael, Spyros Tragoudas
    ATPG for Path Delay Faults without Path Enumeration. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:384-0 [Conf]
  44. Maria K. Michael, Spyros Tragoudas
    Generation of Hazard Identification Functions. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:419-424 [Conf]
  45. Saravanan Padmanaban, Spyros Tragoudas
    An Adaptive Path Delay Fault Diagnosis Methodology. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:491-496 [Conf]
  46. Krishna Prasad Raghuraman, Haibo Wang, Spyros Tragoudas
    Minimizing FPGA Reconfiguration Data at Logic Level. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:219-224 [Conf]
  47. Khadija Stewart, Themistoklis Haniotakis, Spyros Tragoudas
    Design and Evaluation of a Security Scheme for Sensor Networks. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:197-201 [Conf]
  48. M. Welling, Spyros Tragoudas, Haibo Wang
    A Minimum Cut Based Re-Synthesis Approach. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:202-207 [Conf]
  49. Michael N. Skoufis, Haibo Wang, Themistoklis Haniotakis, Spyros Tragoudas
    Glitch Control with Dynamic Receiver Threshold Adjustment. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:410-415 [Conf]
  50. Rajsekhar Adapa, Edward Flanigan, Spyros Tragoudas, Michael Laisne, Hailong Cui, Tsvetomir Petrov
    Function-Based Test Generation for (Non-Robust) Path Delay Faults Using the Launch-off-Capture Scan Architecture. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:717-722 [Conf]
  51. Edward Flanigan, Spyros Tragoudas
    Enhanced Identification of Strong Robustly Testable Paths. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:729-736 [Conf]
  52. Manoj Kumar Goparaju, Spyros Tragoudas
    A Fault Tolerant Design Methodology for Threshold Logic Gates and Its Optimizations. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:420-425 [Conf]
  53. Dimitrios Karayiannis, Spyros Tragoudas
    ATPD: An Automatic Test Pattern Generator for Path Delay Faults. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:443-452 [Conf]
  54. Saravanan Padmanaban, Maria K. Michael, Spyros Tragoudas
    Exact path delay grading with fundamental BDD operations. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:642-651 [Conf]
  55. Saravanan Padmanaban, Spyros Tragoudas
    A Critical Path Selection Method for Delay Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:232-241 [Conf]
  56. Spyros Tragoudas
    Accurate path delay fault coverage is feasible. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:201-210 [Conf]
  57. Haibo Wang, Suchitra Kulkarni, Spyros Tragoudas
    On-line Testing Field Programmable Analog Array Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:1340-1348 [Conf]
  58. Arkan Abdulrahman, Spyros Tragoudas
    Compact ATPG for Concurrent SOC Testing. [Citation Graph (0, 0)][DBLP]
    MTV, 2004, pp:16-21 [Conf]
  59. M. Moiz Khan, Spyros Tragoudas, Magdy S. Abadir, Jiang Brandon Liu
    Identification of Gates for Covering all Critical Paths. [Citation Graph (0, 0)][DBLP]
    MTV, 2004, pp:92-96 [Conf]
  60. Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis
    Mapping Computational Intensive Applications to a New Coarse-Grained Reconfigurable Data-Path. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:652-661 [Conf]
  61. Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Costas E. Goutis
    A Novel Data-Path for Accelerating DSP Kernels. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:363-372 [Conf]
  62. Turgay Korkmaz, Marwan Krunz, Spyros Tragoudas
    An efficient algorithm for finding a path subject to two additive constraints. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS, 2000, pp:318-327 [Conf]
  63. Frank Thomson Leighton, Fillia Makedon, Serge A. Plotkin, Clifford Stein, Éva Tardos, Spyros Tragoudas
    Fast Approximation Algorithms for Multicommodity Flow Problems [Citation Graph (0, 0)][DBLP]
    STOC, 1991, pp:101-111 [Conf]
  64. Jim E. Crenshaw, Spyros Tragoudas, Naveed A. Sherwani
    High Performance Over-the-Cell Routing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:137-142 [Conf]
  65. Krishna Prasad Raghuraman, Haibo Wang, Spyros Tragoudas
    A Novel Approach to Minimizing Reconfiguration Cost for LUT-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:673-676 [Conf]
  66. Edward Flanigan, Rajsekhar Adapa, Hailong Cui, Michael Laisne, Spyros Tragoudas, Tsvetomir Petrov
    Function-based ATPG for Path Delay Faults using the Launch-Off-Capture Scan Architecture. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:805-812 [Conf]
  67. Dimitrios Kagaris, Spyros Tragoudas
    Generating deterministic unordered test patterns with counters. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:374-379 [Conf]
  68. Dimitrios Karayiannis, Spyros Tragoudas
    A Nonenumerative ATPG for Functionally Sensitizable Path Delay Faults. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:440-445 [Conf]
  69. Khadija Stewart, Spyros Tragoudas
    Interconnect Testing for Networks on Chips. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:100-107 [Conf]
  70. Rajsekhar Adapa, Spyros Tragoudas, Maria K. Michael
    Accelerating Diagnosis via Dominance Relations between Sets of Faults. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:219-224 [Conf]
  71. Dimitrios Kagaris, Spyros Tragoudas, Grammati E. Pantziou, Christos D. Zaroliagis
    On the Computation of Fast Data Transmissions in Networks with Capacities and Delays. [Citation Graph (0, 0)][DBLP]
    WADS, 1995, pp:291-302 [Conf]
  72. Fillia Makedon, Spyros Tragoudas
    Approximating the minimum net expansion: Near optimal solutions to circuit partitioning problems. [Citation Graph (0, 0)][DBLP]
    WG, 1990, pp:140-153 [Conf]
  73. Spyros Tragoudas, Yaakov L. Varol
    Computing Disjoint Path with Lenght Constraints. [Citation Graph (0, 0)][DBLP]
    WG, 1996, pp:375-389 [Conf]
  74. Turgay Korkmaz, Marwan Krunz, Spyros Tragoudas
    An efficient algorithm for finding a path subject to two additive constraints. [Citation Graph (0, 0)][DBLP]
    Computer Communications, 2002, v:25, n:3, pp:225-238 [Journal]
  75. Dimitrios Kagaris, Spyros Tragoudas
    Computational analysis of counter-based schemes for VLSI test pattern generation. [Citation Graph (0, 0)][DBLP]
    Discrete Applied Mathematics, 2001, v:110, n:2-3, pp:227-250 [Journal]
  76. James Haralambides, Spyros Tragoudas
    Bipartitioning into Overlapping Sets. [Citation Graph (0, 0)][DBLP]
    Int. J. Found. Comput. Sci., 1995, v:6, n:1, pp:67-88 [Journal]
  77. Antonios Symvonis, Spyros Tragoudas
    Searching a Pseudo 3-Sided Solid Orthoconvex Grid. [Citation Graph (0, 0)][DBLP]
    Int. J. Found. Comput. Sci., 1993, v:4, n:4, pp:325-353 [Journal]
  78. Dimitri Kagaris, Spyros Tragoudas
    Maximum weighted independent sets on transitive graphs and applications1. [Citation Graph (0, 0)][DBLP]
    Integration, 1999, v:27, n:1, pp:77-86 [Journal]
  79. Dimitri Kagaris, Spyros Tragoudas, Amitava Majumdar
    Test-set partitioning for multi-weighted random LFSRs. [Citation Graph (0, 0)][DBLP]
    Integration, 2000, v:30, n:1, pp:65-75 [Journal]
  80. Spyros Tragoudas, Dimitrios Karayiannis
    Implementing and clustering modules with complex delays. [Citation Graph (0, 0)][DBLP]
    Integration, 1997, v:22, n:1-2, pp:39-57 [Journal]
  81. Spyros Tragoudas, Yaakov L. Varol
    Disjoint Paths with Length Constraints. [Citation Graph (0, 0)][DBLP]
    I. J. Comput. Appl., 2002, v:9, n:3, pp:158-166 [Journal]
  82. Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Constantinos E. Goutis
    A Reconfigurable Coarse-grain Data-path for Accelerating Computational Intensive Kernels. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2005, v:14, n:4, pp:877-893 [Journal]
  83. Frank Thomson Leighton, Fillia Makedon, Serge A. Plotkin, Clifford Stein, Éva Stein, Spyros Tragoudas
    Fast Approximation Algorithms for Multicommodity Flow Problems. [Citation Graph (0, 0)][DBLP]
    J. Comput. Syst. Sci., 1995, v:50, n:2, pp:228-243 [Journal]
  84. Panayiotis E. Pintelas, Spyros Tragoudas
    A comparative study of five language independent programming environments. [Citation Graph (0, 0)][DBLP]
    Journal of Systems and Software, 1991, v:14, n:1, pp:3-15 [Journal]
  85. Spyros Tragoudas
    Improved Approximations for the Minimum-Cut Ratio and the Flux. [Citation Graph (0, 0)][DBLP]
    Mathematical Systems Theory, 1996, v:29, n:2, pp:157-167 [Journal]
  86. Dimitrios Kagaris, Grammati E. Pantziou, Spyros Tragoudas, Christos D. Zaroliagis
    Transmissions in a network with capacities and delays. [Citation Graph (0, 0)][DBLP]
    Networks, 1999, v:33, n:3, pp:167-174 [Journal]
  87. Dimitrios Kagaris, Spyros Tragoudas
    Retiming-Based Partial Scan. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:1, pp:75-87 [Journal]
  88. Dimitri Kagaris, Spyros Tragoudas, Sherin Kuriakose
    InTeRail: A Test Architecture for Core-Based SOCs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:2, pp:137-149 [Journal]
  89. Dimitrios Kagaris, Spyros Tragoudas, Amitava Majumdar
    On the Use of Counters for Reproducing Deterministic Test Sets. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:12, pp:1405-1419 [Journal]
  90. Spyros Tragoudas
    Min-Cut Partitioning on Underlying Tree and Graph Structures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:4, pp:470-474 [Journal]
  91. Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Constantinos E. Goutis
    A high-performance data path for synthesizing DSP kernels. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:1154-1162 [Journal]
  92. Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos, Spyros Tragoudas
    A new built-in TPG method for circuits with random patternresistant faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:7, pp:859-866 [Journal]
  93. M. Moiz Khan, Spyros Tragoudas
    Rewiring for watermarking digital circuit netlists. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:7, pp:1132-1137 [Journal]
  94. Dimitrios Kagaris, Fillia Makedon, Spyros Tragoudas
    A method for pseudo-exhaustive test pattern generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:9, pp:1170-1178 [Journal]
  95. Dimitrios Kagaris, Spyros Tragoudas
    On the nonenumerative path delay fault simulation problem. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:9, pp:1095-1101 [Journal]
  96. Dimitrios Kagaris, Spyros Tragoudas
    On the design of optimal counter-based schemes for test set embedding. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:2, pp:219-230 [Journal]
  97. Dimitrios Kagaris, Spyros Tragoudas, Dinesh Bhatia
    Pseudo-exhaustive built-in TPG for sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:9, pp:1160-1171 [Journal]
  98. Dimitrios Kagaris, Spyros Tragoudas, Dimitrios Karayiannis
    Improved nonenumerative path-delay fault-coverage estimation based on optimal polynomial-time algorithms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:3, pp:309-315 [Journal]
  99. Maria K. Michael, Themistoklis Haniotakis, Spyros Tragoudas
    A unified framework for generating all propagation functions for logic errors and events. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:6, pp:980-986 [Journal]
  100. Saravanan Padmanaban, Maria K. Michael, Spyros Tragoudas
    Exact path delay fault coverage with fundamental ZBDD operations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:3, pp:305-316 [Journal]
  101. Saravanan Padmanaban, Spyros Tragoudas
    An implicit path-delay fault diagnosis methodology. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:10, pp:1399-1408 [Journal]
  102. Saravanan Padmanaban, Spyros Tragoudas
    Efficient identification of (critical) testable path delay faults using decision diagrams. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:1, pp:77-87 [Journal]
  103. Spyros Tragoudas, Dimitrios Karayiannis
    A fast nonenumerative automatic test pattern generator for pathdelay faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:7, pp:1050-1057 [Journal]
  104. Spyros Tragoudas, Vijay Nagarandal
    On-chip embedding mechanisms for large sets of vectors for delay test. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:3, pp:488-497 [Journal]
  105. Dimitrios Kagaris, Spyros Tragoudas
    Von Neumann hybrid cellular automata for generating deterministic test sequences. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2001, v:6, n:3, pp:308-321 [Journal]
  106. Dimitrios Kagaris, Spyros Tragoudas
    A fast algorithm for minimizing FPGA combinational and sequential modules. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1996, v:1, n:3, pp:341-351 [Journal]
  107. Maria K. Michael, Spyros Tragoudas
    ATPG tools for delay faults at the functional level. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:1, pp:33-57 [Journal]
  108. Spyros Tragoudas, N. Denny
    Path delay fault testing using test points. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2003, v:8, n:1, pp:1-10 [Journal]
  109. Saravanan Padmanaban, Spyros Tragoudas
    Implicit grading of multiple path delay faults. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:2, pp:346-361 [Journal]
  110. J. V. Deodhar, Spyros Tragoudas
    Implicit deductive fault simulation for complex delay fault models. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:6, pp:636-641 [Journal]
  111. Maria K. Michael, Spyros Tragoudas
    Function-based compact test pattern generation for path delay faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:8, pp:996-1001 [Journal]
  112. Spyros Tragoudas, Yaakov L. Varol
    Disjoint paths with length constraints. [Citation Graph (0, 0)][DBLP]
    Computers and Their Applications, 1999, pp:277-280 [Conf]
  113. Rajsekhar Adapa, Spyros Tragoudas, Maria K. Michael
    Sub-faults identification for collapsing in diagnosis. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  114. Spyros Tragoudas
    The most reliable data path transmission. [Citation Graph (0, 0)][DBLP]
    IPCCC, 1999, pp:15-19 [Conf]
  115. Khadija Stewart, Spyros Tragoudas
    Managing the power resources of sensor networks with performance considerations. [Citation Graph (0, 0)][DBLP]
    Computer Communications, 2007, v:30, n:5, pp:1122-1135 [Journal]
  116. Michalis D. Galanis, Gregory Dimitroulakos, Spyros Tragoudas, Costas E. Goutis
    Speedups in embedded systems with a high-performance coprocessor datapath. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:3, pp:- [Journal]
  117. Dimitrios Kagaris, Spyros Tragoudas
    Cost-effective LFSR synthesis for optimal pseudoexhaustive BIST test sets. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:4, pp:526-536 [Journal]
  118. M. M. Vaseekar Kumar, Spyros Tragoudas
    Low Power Test Generation for Path Delay Faults. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2005, v:1, n:2, pp:194-205 [Journal]

  119. Cellular automata for generating deterministic test sequences. [Citation Graph (, )][DBLP]


  120. Scalable codeword generation for coupled buses. [Citation Graph (, )][DBLP]


  121. A Fault Tolerance Aware Synthesis Methodology for Threshold Logic Gate Networks. [Citation Graph (, )][DBLP]


  122. Prioritization of Paths for Diagnosis. [Citation Graph (, )][DBLP]


  123. Gating internal nodes to reduce power during scan shift. [Citation Graph (, )][DBLP]


  124. Scalable identification of threshold logic functions. [Citation Graph (, )][DBLP]


  125. Propagation of Transients Along Sensitizable Paths. [Citation Graph (, )][DBLP]


  126. Sequential Path Delay Fault Identification Using Encoded Delay Propagation Signatures. [Citation Graph (, )][DBLP]


  127. A Novel Test Generation Methodology for Adaptive Diagnosis. [Citation Graph (, )][DBLP]


  128. A High-Performance Bus Architecture for Strongly Coupled Interconnects. [Citation Graph (, )][DBLP]


  129. A novel probabilistic SET propagation method. [Citation Graph (, )][DBLP]


  130. A Novel ATPG Framework to Detect Weight Related Defects in Threshold Logic Gates. [Citation Graph (, )][DBLP]


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