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Bing J. Sheu: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Andrew B. Kahng, Bing J. Sheu, Nancy Nettleton, John M. Cohn, Shekhar Borkar, Louis Scheffer, Ed Cheng, Sang Wang
    Panel: Is Nanometer Design Under Control? [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:591-592 [Conf]
  2. Oscal T.-C. Chen, Z. Zhang, Bing J. Sheu
    An Adaptive High-Speed Lossy Data Compression. [Citation Graph (0, 0)][DBLP]
    Data Compression Conference, 1992, pp:349-358 [Conf]
  3. Wai-Chi Fang, Bing J. Sheu, Oscal T.-C. Chen
    A Neural Network Based VLSI Vector Quantizer for Real-Time Image Compression. [Citation Graph (0, 0)][DBLP]
    Data Compression Conference, 1991, pp:342-351 [Conf]
  4. David C. Chen, Bing J. Sheu, Theodore W. Berger
    A Compact Neural Network Based CDMA Receiver for Multimedia Wireless Communication. [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:99-0 [Conf]
  5. Joongho Choi, Bing J. Sheu
    A GaAs Receiver Module for Optoelectronic Computing and Interconnection. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:494-497 [Conf]
  6. Eric Y. Chou, Bing J. Sheu, Tony H. Wu, Robert C. Chang
    VLSI design of densely-connected array processors. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:492-497 [Conf]
  7. Wai-Chi Fang, Bing J. Sheu, Holger Venus, Rainer Sandau
    Smart-pixel array processors based on optimal cellular neural networks for space sensor applications. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:703-0 [Conf]
  8. Wai-Chi Fang, Guang Yang, Bedabrata Pain, Bing J. Sheu
    A Low Power Smart Vision System Based on Active Pixel Sensor Integrated with Programmable Neural Processor. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:429-434 [Conf]
  9. Wen-Jay Hsu, Bing J. Sheu, Sudhir M. Gowda
    Testing of Analog Neural Array-Processor Chips. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:118-121 [Conf]
  10. Yoondong Park, Jim-Shih Liaw, Theodore W. Berger, Bing J. Sheu
    Compact VLSI Neural Network Circuit with High-Capacity Dynamic Synapses. [Citation Graph (0, 0)][DBLP]
    IJCNN (4), 2000, pp:214-218 [Conf]
  11. Sa Hyun Bang, Bing J. Sheu, Josephine C.-F. Chang
    Search of Optimal Solutions in Multi-Level Neural Networks. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:423-426 [Conf]
  12. Robert C.-H. Chang, Bing J. Sheu
    An Analog MOS Model for Circuit Simulation and Benchmark Test Results. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:311-314 [Conf]
  13. Joongho Choi, Bing J. Sheu, Josephine C.-F. Chang
    A Gaussian Synapse Circuit for Analog VLSI Neural Networks. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:483-486 [Conf]
  14. Bing J. Sheu
    Constructing Intelligent Microsystems with Modular VLSI Networks Design. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:2100-2103 [Conf]
  15. Bing J. Sheu, Sa H. Bang, Wai-Chi Fang
    VLSI Design of Cellular Neutral Networks with Annealing and Optical Input Capabilities. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:653-656 [Conf]
  16. Bing J. Sheu, Theodore W. Berger, Tony H. Wu, Richard H. Tsai
    VLSI Neural Network Implementation of a Hippocampal Model. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:1664-1667 [Conf]
  17. Bing J. Sheu, Robert C. Chang, Tony H. Wu, Sa H. Bang
    VLSI-Compatible Cellular Neural Networks with Optimal Solution Capability for Optimization. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:1165-1168 [Conf]
  18. Yoondong Park, Steve H. Jen, Bing J. Sheu, Heesook Yoon, In Gyeom Kim
    An efficient parameter extraction method using statistical optimization in S-CMOS deep-submicron/nanometer model. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:233-236 [Conf]
  19. Oscal T.-C. Chen, Bing J. Sheu, Wai-Chi Fang
    Image Compression on a VLSI Neural-Based Vector Quantizer. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Manage., 1992, v:28, n:6, pp:687-706 [Journal]
  20. Sudhir M. Gowda, Bing J. Sheu
    BSIM plus: an advanced SPICE model for submicron MOS VLSI circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:9, pp:1166-1170 [Journal]
  21. M. C. Hsu, Bing J. Sheu
    Inverse-Geometry Dependence of MOS Transistor Electrical Parameters. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:4, pp:582-585 [Journal]
  22. Steve H. Jen, Bing J. Sheu
    A compact and unified MOS DC current model with highly continuous conductances for low-voltage ICs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:2, pp:169-172 [Journal]
  23. Bing J. Sheu, Wen-Jay Hsu, P. K. Ko
    An MOS transistor charge model for VLSI design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:4, pp:520-527 [Journal]
  24. Chung-Ping Wan, Bing J. Sheu, Shih-Lien Lu
    Device and circuit simulation interface for an integrated VLSI design environment. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:9, pp:998-1004 [Journal]
  25. Wai-Chi Fang, Chi-Yung Chang, Bing J. Sheu, Oscal T.-C. Chen, J. C. Curlander
    VLSI systolic binary tree-searched vector quantizer for image compression. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:1, pp:33-44 [Journal]
  26. Joongho Choi, Bing J. Sheu, Josephine C.-F. Chang
    A Gaussian synapse circuit for analog VLSI neural networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:1, pp:129-133 [Journal]

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