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Yehia Massoud: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Mattan Kamon, Nuno Alexandre Marques, Yehia Massoud, Luis Miguel Silveira, Jacob White
    Interconnect Analysis: From 3-D Structures to Circuit Models. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:910-914 [Conf]
  2. Yehia Massoud, Jamil Kawa, Don MacMillen, Jacob White
    Modeling and Analysis of Differential Signaling for Minimizing Inductive Cross-Talk. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:804-809 [Conf]
  3. Yehia Massoud, Steve S. Majors, Tareq Bustami, Jacob White
    Layout Techniques for Minimizing On-Chip Interconnect Self Inductance. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:566-571 [Conf]
  4. Yehia Massoud, Jacob White
    Improving the generality of the fictitious magnetic charge approach to computing inductances in the presence of permeable materials. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:552-555 [Conf]
  5. Arthur Nieuwoudt, Yehia Massoud
    Multi-level approach for integrated spiral inductor optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:648-651 [Conf]
  6. Arthur Nieuwoudt, Tamer Ragheb, Yehia Massoud
    SOC-NLNA: synthesis and optimization for fully integrated narrow-band CMOS low noise amplifiers. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:879-884 [Conf]
  7. Mohamed El-Nozahi, Yehia Massoud
    An integrated circuit/behavioral simulation framework for continuous-time sigma-delta ADCs. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:353-356 [Conf]
  8. Tamer Ragheb, Arthur Nieuwoudt, Yehia Massoud
    Efficient modeling of integrated narrow-band low noise amplifiers for design space exploration. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:187-191 [Conf]
  9. Yehia Massoud, Jacob White
    FastMag: a 3-D magnetostatic inductance extraction program for structures with permeable materials. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:478-484 [Conf]
  10. Mosin Mondal, Yehia Massoud
    Reducing pessimism in RLC delay estimation using an accurate analytical frequency dependent model for inductance. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:691-696 [Conf]
  11. Arthur Nieuwoudt, Yehia Massoud
    Robust automated synthesis methodology for integrated spiral inductors with variability. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:502-507 [Conf]
  12. Soyoung Kim, Yehia Massoud, S. Simon Wong
    On the Accuracy of Return Path Assumption for Loop Inductance Extraction for 0.1?m Technology and Beyond. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:401-404 [Conf]
  13. Mosin Mondal, Tamer Ragheb, Xiang Wu, Adnan Aziz, Yehia Massoud
    Provisioning On-Chip Networks under Buffered RC Interconnect Delay Variations. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:873-878 [Conf]
  14. Arthur Nieuwoudt, Tamer Ragheb, Hamid Nejati, Yehia Massoud
    Increasing Manufacturing Yield for Wideband RF CMOS LNAs in the Presence of Process Variations. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:801-806 [Conf]
  15. Arthur Nieuwoudt, Yehia Massoud
    Assessing the Implications of Process Variations on Future Carbon Nanotube Bundle Interconnect Solutions. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:119-126 [Conf]
  16. Mosin Mondal, Andrew J. Ricketts, Sami Kirolos, Tamer Ragheb, Greg M. Link, Narayanan Vijaykrishnan, Yehia Massoud
    Mitigating Thermal Effects on Clock Skew with Dynamically Adaptive Drivers. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:67-72 [Conf]
  17. Mosin Mondal, Kartik Mohanram, Yehia Massoud
    Parameter-Variation-Aware Analysis for Noise Robustness. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:655-659 [Conf]
  18. Mehboob Alam, Arthur Nieuwoudt, Yehia Massoud
    Wavelet-Based Passivity Preserving Model Order Reduction for Wideband Interconnect Characterization. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:432-437 [Conf]
  19. Arthur Nieuwoudt, Tamer Ragheb, Yehia Massoud
    Systematic Design Optimization Methodology for Multi-Band CMOS Low Noise Amplifiers. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:139-144 [Conf]
  20. Soumya Eachempati, Narayanan Vijaykrishnan, Arthur Nieuwoudt, Yehia Massoud
    Impact of Process Variations on Carbon Nanotube Bundle Interconnect for Future FPGA Architectures. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:516-517 [Conf]
  21. Yehia Massoud, Arthur Nieuwoudt
    Modeling and design challenges and solutions for carbon nanotube-based interconnect in future high performance integrated circuits. [Citation Graph (0, 0)][DBLP]
    JETC, 2006, v:2, n:3, pp:155-196 [Journal]
  22. Qing Su, Jamil Kawa, Charles Chiang, Yehia Massoud
    Accurate modeling of substrate resistive coupling for floating substrates. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:1, pp:44-51 [Journal]
  23. Mosin Mondal, Andrew J. Ricketts, Sami Kirolos, Tamer Ragheb, Greg M. Link, Narayanan Vijaykrishnan, Yehia Massoud
    Thermally robust clocking schemes for 3D integrated circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1206-1211 [Conf]
  24. Soumya Eachempati, Arthur Nieuwoudt, Aman Gayasen, Narayanan Vijaykrishnan, Yehia Massoud
    Assessing carbon nanotube bundle interconnect for future FPGA architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:307-312 [Conf]
  25. Mehboob Alam, Arthur Nieuwoudt, Yehia Massoud
    Wavelet-Based Interpolation Point Selection for Multi-Shifted Arnoldi. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:653-656 [Conf]
  26. Mosin Mondal, Sami Kirolos, Yehia Massoud
    Estimation of Capacitive Crosstalk-Induced Short-Circuit Energy. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:897-900 [Conf]
  27. Jason N. Laska, Sami Kirolos, Marco F. Duarte, Tamer Ragheb, Richard G. Baraniuk, Yehia Massoud
    Theory and Implementation of an Analog-to-Information Converter using Random Demodulation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1959-1962 [Conf]
  28. Yehia Massoud, Arthur Nieuwoudt, Tamer Ragheb
    Variability-Aware Synthesis for Wideband Low Noise Amplifiers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3219-3222 [Conf]
  29. Hamid Nejati, Tamer Ragheb, Arthur Nieuwoudt, Yehia Massoud
    Modeling and Design of Ultrawideband Low Noise Amplifiers with Generalized Impedance Matching Networks. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2622-2625 [Conf]
  30. Amir Hosseini, Yehia Massoud
    Subwavelength Plasmonic Bragg Reflector Structures for On-chip Optoelectronic Applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2283-2286 [Conf]
  31. Xiang Wu, Tamer Ragheb, Adnan Aziz, Yehia Massoud
    Implementing DSP Algorithms with On-Chip Networks. [Citation Graph (0, 0)][DBLP]
    NOCS, 2007, pp:307-316 [Conf]
  32. Mosin Mondal, Yehia Massoud
    Accurate Loop Self Inductance Bound for Efficient Inductance Screening. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:12, pp:1393-1397 [Journal]
  33. Yehia Massoud, Jacob K. White
    Simulation and modeling of the effect of substrate conductivity on coupling inductance and circuit crosstalk. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:3, pp:286-291 [Journal]
  34. Yehia Massoud, Steve S. Majors, Jamil Kawa, Tareq Bustami, Don MacMillen, Jacob K. White
    Managing on-chip inductive effects. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:789-798 [Journal]

  35. Predicting the Performance and Reliability of Carbon Nanotube Bundles for On-Chip Interconnect. [Citation Graph (, )][DBLP]


  36. Hierarchical Optimization Methodology for Wideband Low Noise Amplifiers. [Citation Graph (, )][DBLP]


  37. Frequency Selective Model Order Reduction via Spectral Zero Projection. [Citation Graph (, )][DBLP]


  38. Reduced-Order Wide-Band Interconnect Model Realization using Filter-Based Spline Interpolation. [Citation Graph (, )][DBLP]


  39. Automated design of tunable impedance matching networks for reconfigurable wireless applications. [Citation Graph (, )][DBLP]


  40. Impact of dummy filling techniques on interconnect capacitance and planarization in nano-scale process technology. [Citation Graph (, )][DBLP]


  41. On the design of customizable low-voltage common-gate LNA-mixer pair using current and charge reusing techniques. [Citation Graph (, )][DBLP]


  42. Robust reconfigurable filter design using analytic variability quantification techniques. [Citation Graph (, )][DBLP]


  43. On the modeling of resistance in graphene nanoribbon (GNR) for future interconnect applications. [Citation Graph (, )][DBLP]


  44. Performance analysis of optimized carbon nanotube interconnect. [Citation Graph (, )][DBLP]


  45. Power-supply-variation-aware timing analysis of synchronous systems. [Citation Graph (, )][DBLP]


  46. Analytical modeling of common-gate low noise amplifiers. [Citation Graph (, )][DBLP]


  47. Robust wide range of supply-voltage operation using continuous adaptive size-ratio gates. [Citation Graph (, )][DBLP]


  48. On the feasibility of hardware implementation of sub-Nyquist random-sampling based analog-to-information conversion. [Citation Graph (, )][DBLP]


  49. Accurate analytical delay modeling of CMOS clock buffers considering power supply variations. [Citation Graph (, )][DBLP]


  50. A fault-aware dynamic routing algorithm for on-chip networks. [Citation Graph (, )][DBLP]


  51. An Analytical model for characteristic impedance in nanostrip plasmonic waveguides. [Citation Graph (, )][DBLP]


  52. Investigating the Design, Performance, and Reliability of Multi-Walled Carbon Nanotube Interconnect. [Citation Graph (, )][DBLP]


  53. Investigating the Impact of Fill Metal on Crosstalk-Induced Delay and Noise. [Citation Graph (, )][DBLP]


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