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Rouwaida Kanj: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Rouwaida Kanj, Rajiv V. Joshi, Sani R. Nassif
    Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:69-72 [Conf]
  2. Rouwaida Kanj, Timothy Lehner, Bhavna Agrawal, Elyse Rosenbaum
    Noise characterization of static CMOS gates. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:888-893 [Conf]
  3. Rouwaida Kanj, Elyse Rosenbaum
    A critical look at design guidelines for SOI logic gates. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2002, pp:261-264 [Conf]
  4. Praveen Elakkumanan, Jente B. Kuang, Kevin J. Nowka, Ramalingam Sridhar, Rouwaida Kanj, Sani R. Nassif
    SRAM Local Bit Line Access Failure Analyses. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:204-209 [Conf]
  5. Fadi J. Kurdahi, Ahmed M. Eltawil, Young-Hwan Park, Rouwaida N. Kanj, Sani R. Nassif
    System-Level SRAM Yield Enhancement. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:179-184 [Conf]
  6. Rouwaida Kanj, Rajiv V. Joshi, Jayakumaran Sivagnaname, Jente B. Kuang, Dhruva Acharyya, Tuyet Nguyen, Chandler McDowell, Sani R. Nassif
    Gate Leakage Effects on Yield and Design Considerations of PD/SOI SRAM Designs. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:33-40 [Conf]
  7. Amin Khajeh Djahromi, Ahmed M. Eltawil, Fadi J. Kurdahi, Rouwaida Kanj
    Cross Layer Error Exploitation for Aggressive Voltage Scaling. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:192-197 [Conf]
  8. Rouwaida Kanj, Elyse Rosenbaum
    Critical evaluation of SOI design guidelines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:9, pp:885-894 [Journal]

  9. Yield estimation of SRAM circuits using "Virtual SRAM Fab". [Citation Graph (, )][DBLP]

  10. An elegant hardware-corroborated statistical repair and test methodology for conquering aging effects. [Citation Graph (, )][DBLP]

  11. A floating-body dynamic supply boosting technique for low-voltage sram in nanoscale PD/SOI CMOS technologies. [Citation Graph (, )][DBLP]

  12. SRAM methodology for yield and power efficiency: per-element selectable supplies and memory reconfiguration schemes. [Citation Graph (, )][DBLP]

  13. Statistical leakage modeling for accurate yield analysis: the CDF matching method and its alternatives. [Citation Graph (, )][DBLP]

  14. Statistical Evaluation of Split Gate Opportunities for Improved 8T/6T Column-Decoupled SRAM Cell Yield. [Citation Graph (, )][DBLP]

  15. A Root-Finding Method for Assessing SRAM Stability. [Citation Graph (, )][DBLP]

  16. Statistical yield analysis of silicon-on-insulator embedded DRAM. [Citation Graph (, )][DBLP]

  17. The impact of BEOL lithography effects on the SRAM cell performance and yield. [Citation Graph (, )][DBLP]

  18. Use of scalable Parametric Measurement Macro to improve semiconductor technology characterization and product test. [Citation Graph (, )][DBLP]

  19. FinFET SRAM Design. [Citation Graph (, )][DBLP]

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