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Jerzy Tyszer: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Mark Kassab, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
    Software Accelerated Functional Fault Simulation for Data-Path Architectures. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:333-338 [Conf]
  2. Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
    Test response compactor with programmable selector. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:1089-1094 [Conf]
  3. Sanjay Gupta, Janusz Rajski, Jerzy Tyszer
    Test pattern generation based on arithmetic operations. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:117-124 [Conf]
  4. Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
    On testable multipliers for fixed-width data path architectures. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:541-547 [Conf]
  5. Janusz Rajski, Jerzy Tyszer, Babak Salimi
    On the Diagnostic Resolution of Signature Analysis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:364-367 [Conf]
  6. Chen Wang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Jerzy Tyszer
    On Compacting Test Response Data Containing Unknown Values. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:855-862 [Conf]
  7. Janusz Rajski, Jerzy Tyszer
    Test Data Compression and Compaction for Embedded Test of Nanometer Technology Designs. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:331-0 [Conf]
  8. Janusz Rajski, Jerzy Tyszer
    The detection of small size multiple faults by single fault test sets n programmable logic arrays. [Citation Graph (0, 0)][DBLP]
    Fehlertolerierende Rechensysteme, 1984, pp:417-425 [Conf]
  9. Mark Kassab, Janusz Rajski, Jerzy Tyszer
    Hierarchical Functional-Fault Simulation for High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:596-605 [Conf]
  10. Grzegorz Mrugalski, Jerzy Tyszer, Janusz Rajski
    Synthesis of pattern generators based on cellular automata with phase shifters. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:368-377 [Conf]
  11. Grzegorz Mrugalski, Chen Wang, Artur Pogiel, Jerzy Tyszer, Janusz Rajski
    Fault Diagnosis in Designs with Convolutional Compactors. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:498-507 [Conf]
  12. Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
    Parameterizable Testing Scheme for FIR Filters. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:694-703 [Conf]
  13. Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee, Rob Thompson, Kun-Han Tsai, Andre Hertwig, Nagesh Tamarapalli, Grzegorz Mrugalski, Geir Eide, Jun Qian
    Embedded Deterministic Test for Low-Cost Manufacturing Test. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:301-310 [Conf]
  14. Janusz Rajski, Jerzy Tyszer
    Fault Diagnosis in Scan-Based BIST. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:894-902 [Conf]
  15. Janusz Rajski, Jerzy Tyszer
    Modular logic built-in self-test for IP cores. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:313-0 [Conf]
  16. Janusz Rajski, Nagesh Tamarapalli, Jerzy Tyszer
    Automated synthesis of large phase shifters for built-in self-test. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:1047-1056 [Conf]
  17. Janusz Rajski, Jerzy Tyszer, Chen Wang, Sudhakar M. Reddy
    Convolutional Compaction of Test Responses. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:745-754 [Conf]
  18. Nadime Zacharia, Janusz Rajski, Jerzy Tyszer, John A. Waicukauski
    Two-Dimensional Test Data Decompressor for Multiple Scan Designs. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:186-194 [Conf]
  19. Janusz Rajski, Nilanjan Mukherjee, Jerzy Tyszer, Thomas Rinderknecht
    Embedded Test for Low Cost Manufacturing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:21-23 [Conf]
  20. Janusz Rajski, Jerzy Tyszer, Sanjay Patel
    Built-In Self-Test for Systems on Silicon. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:609-610 [Conf]
  21. Huaxing Tang, Chen Wang, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Irith Pomeranz
    On Efficient X-Handling Using a Selective Compaction Scheme to Achieve High Test Response Compaction Ratios. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:59-64 [Conf]
  22. Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
    Planar High Performance Ring Generators. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:193-198 [Conf]
  23. Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
    High Speed Ring Generators and Compactors of Test Data. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:57-62 [Conf]
  24. Grzegorz Mrugalski, Jerzy Tyszer, Janusz Rajski
    Linear Independence as Evaluation Criterion for Two-Dimensional Test Pattern Generators. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:377-388 [Conf]
  25. Nilanjan Mukherjee, H. Kassab, Janusz Rajski, Jerzy Tyszer
    Arithmetic built-in self test for high-level synthesis. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:132-139 [Conf]
  26. Janusz Rajski, Grzegorz Mrugalski, Jerzy Tyszer
    Comparative Study of CA-based PRPGs and LFSRs with Phase Shifters. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:236-245 [Conf]
  27. Janusz Rajski, Jerzy Tyszer
    Synthesis of X-Tolerant Convolutional Compactors. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:114-119 [Conf]
  28. Janusz Rajski, Jerzy Tyszer
    Design of Phase Shifters for BIST Applications. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:218-224 [Conf]
  29. Nadime Zacharia, Janusz Rajski, Jerzy Tyszer
    Decompression of test data using variable-length seed LFSRs. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:426-433 [Conf]
  30. Dariusz Czysz, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
    Low Power Embedded Deterministic Test. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:75-83 [Conf]
  31. Grzegorz Mrugalski, Jerzy Tyszer, Janusz Rajski
    2D Test Sequence Generators. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:1, pp:51-59 [Journal]
  32. Janusz Rajski, Mark Kassab, Nilanjan Mukherjee, Nagesh Tamarapalli, Jerzy Tyszer, Jun Qian
    Embedded Deterministic Test for Low-Cost Manufacturing. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:5, pp:58-66 [Journal]
  33. Andrzej Jajszczyk, Jerzy Tyszer
    Broadband Time-Division Circuit Switching. [Citation Graph (0, 0)][DBLP]
    IEEE Journal on Selected Areas in Communications, 1996, v:14, n:2, pp:337-345 [Journal]
  34. Sanjay Gupta, Janusz Rajski, Jerzy Tyszer
    Arithmetic Additive Generators of Pseudo-Exhaustive Test Patterns. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:8, pp:939-949 [Journal]
  35. Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
    High Performance Dense Ring Generators. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:1, pp:83-87 [Journal]
  36. Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
    Testing Schemes for FIR Filter Structures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:7, pp:674-688 [Journal]
  37. Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
    Design of Testable Multipliers for Fixed-Width Data Paths. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1997, v:46, n:7, pp:795-810 [Journal]
  38. Janusz Rajski, Jerzy Tyszer
    Combinatorial Approach to Multiple Contact Faults Coverage in Programmable Logic Arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1985, v:34, n:6, pp:549-553 [Journal]
  39. Janusz Rajski, Jerzy Tyszer
    The Influence of Masking Phenomenon on Coverage Capability of Single Fault Test Sets in PLA's. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1986, v:35, n:1, pp:81-85 [Journal]
  40. Janusz Rajski, Jerzy Tyszer
    Accumulator-Based Compaction of Test Responses. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1993, v:42, n:6, pp:643-650 [Journal]
  41. Janusz Rajski, Jerzy Tyszer
    Recursive Pseudoexhaustive Test Pattern Generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1993, v:42, n:12, pp:1517-1521 [Journal]
  42. Janusz Rajski, Jerzy Tyszer
    On Linear Dependencies in Subspaces of LFSR-Generated Sequences. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:10, pp:1212-1216 [Journal]
  43. Janusz Rajski, Jerzy Tyszer
    Diagnosis of Scan Cells in BIST Environment. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:7, pp:724-731 [Journal]
  44. Janusz Rajski, Jerzy Tyszer, Nadime Zacharia
    Test Data Decompression for Multiple Scan Designs with Boundary Scan. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:11, pp:1188-1200 [Journal]
  45. Jerzy Tyszer
    A Multiple Fault-Tolerant Processor Network Architecture for Pipeline Computing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1988, v:37, n:11, pp:1414-1418 [Journal]
  46. Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
    Cellular automata-based test pattern generators with phase shifters. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:8, pp:878-893 [Journal]
  47. Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
    Ring generators - new devices for embedded test applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:9, pp:1306-1320 [Journal]
  48. Katarzyna Radecka, Janusz Rajski, Jerzy Tyszer
    Arithmetic built-in self-test for DSP cores. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:11, pp:1358-1369 [Journal]
  49. Janusz Rajski, Jerzy Tyszer
    On the diagnostic properties of linear feedback shift registers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:10, pp:1316-1322 [Journal]
  50. Janusz Rajski, Jerzy Tyszer
    Test responses compaction in accumulators with rotate carry adders. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:4, pp:531-539 [Journal]
  51. Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee
    Embedded deterministic test. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:5, pp:776-792 [Journal]
  52. Janusz Rajski, Nagesh Tamarapalli, Jerzy Tyszer
    Automated synthesis of phase shifters for built-in self-testapplications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:10, pp:1175-1188 [Journal]
  53. Janusz Rajski, Jerzy Tyszer, Chen Wang, Sudhakar M. Reddy
    Finite memory test response compactors for embedded test applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:4, pp:622-634 [Journal]
  54. Grzegorz Mrugalski, Janusz Rajski, Dariusz Czysz, Jerzy Tyszer
    New Test Data Decompressor for Low Power Applications. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:539-544 [Conf]
  55. Artur Pogiel, Janusz Rajski, Jerzy Tyszer
    Convolutional Compactors with Variable Polynomials. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:117-122 [Conf]
  56. Grzegorz Mrugalski, Janusz Rajski, Chen Wang, Artur Pogiel, Jerzy Tyszer
    Isolation of Failing Scan Cells through Convolutional Test Response Compaction. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2007, v:23, n:1, pp:35-45 [Journal]

  57. High-Speed On-Chip Event Counters for Embedded Systems. [Citation Graph (, )][DBLP]


  58. Defect Aware to Power Conscious Tests - The New DFT Landscape. [Citation Graph (, )][DBLP]


  59. Diagnosis of failing scan cells through orthogonal response compaction. [Citation Graph (, )][DBLP]


  60. X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis. [Citation Graph (, )][DBLP]


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