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Publications of Author

1. Meenakshi Kaul, Ranga Vemuri, Sriram Govindarajan, Iyad Ouaiss
   An Automated Temporal Partitioning and Loop Fission Approach for FPGA Based Reconfigurable Synthesis of DSP Applications. [Citation Graph (0, 0)][DBLP]
   DAC, 1999, pp:616-622 [Conf]
   
2. Meenakshi Kaul, Ranga Vemuri
   Optimal Temporal Partitioning and Synthesis for Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
   DATE, 1998, pp:389-0 [Conf]
   
3. Meenakshi Kaul, Ranga Vemuri
   Temporal Partitioning combined with Design Space Exploration for Latency Minimization of Run-Time Reconfigured Designs. [Citation Graph (0, 0)][DBLP]
   DATE, 1999, pp:202-209 [Conf]
   
4. Sriram Govindarajan, Iyad Ouaiss, Meenakshi Kaul, Vinoo Srinivasan, Ranga Vemuri
   An Effective Design System for Dynamically Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
   FCCM, 1998, pp:312-313 [Conf]
   
5. Meenakshi Kaul, Ranga Vemuri
   Integrated Block-Processing and Design-Space Exploration in Temporal Partitioning for RTR Architectures. [Citation Graph (0, 0)][DBLP]
   IPPS/SPDP Workshops, 1999, pp:606-615 [Conf]
   
6. Iyad Ouaiss, Sriram Govindarajan, Vinoo Srinivasan, Meenakshi Kaul, Ranga Vemuri
   An Integrated Partitioning and Synthesis System for Dynamically Reconfigurable Multi-FPGA Architectures. [Citation Graph (0, 0)][DBLP]
   IPPS/SPDP Workshops, 1998, pp:31-36 [Conf]
   
7. Ranga Vemuri, Srinivas Katkoori, Meenakshi Kaul, Jay Roy
   An efficient register optimization algorithm for high-level synthesis from hierarchical behavioral specifications. [Citation Graph (0, 0)][DBLP]
   ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:1, pp:189-216 [Journal]