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Publications of Author

1. Meenakshi Kaul, Ranga Vemuri, Sriram Govindarajan, Iyad Ouaiss
   An Automated Temporal Partitioning and Loop Fission Approach for FPGA Based Reconfigurable Synthesis of DSP Applications. [Citation Graph (0, 0)][DBLP]
   DAC, 1999, pp:616-622 [Conf]
   
2. Iyad Ouaiss, Ranga Vemuri
   Efficient Resource Arbitration in Reconfigurable Computing Environments. [Citation Graph (0, 0)][DBLP]
   DATE, 2000, pp:560-566 [Conf]
   
3. Iyad Ouaiss, Ranga Vemuri
   Hierarchical memory mapping during synthesis in FPGA-based reconfigurable computers. [Citation Graph (0, 0)][DBLP]
   DATE, 2001, pp:650-657 [Conf]
   
4. Hassan Al Atat, Iyad Ouaiss
   Register Binding for FPGAs with Embedded Memory. [Citation Graph (0, 0)][DBLP]
   FCCM, 2004, pp:167-175 [Conf]
   
5. Sriram Govindarajan, Iyad Ouaiss, Meenakshi Kaul, Vinoo Srinivasan, Ranga Vemuri
   An Effective Design System for Dynamically Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
   FCCM, 1998, pp:312-313 [Conf]
   
6. Dalia Dagher, Iyad Ouaiss
   Storage Allocation for Diverse FPGA Memory Specifications. [Citation Graph (0, 0)][DBLP]
   FPL, 2004, pp:606-616 [Conf]
   
7. Amit Kasat, Iyad Ouaiss, Ranga Vemuri
   Memory Synthesis for FPGA-Based Reconfigurable Computers. [Citation Graph (0, 0)][DBLP]
   FPL, 2001, pp:70-80 [Conf]
   
8. Iyad Ouaiss, Sriram Govindarajan, Vinoo Srinivasan, Meenakshi Kaul, Ranga Vemuri
   An Integrated Partitioning and Synthesis System for Dynamically Reconfigurable Multi-FPGA Architectures. [Citation Graph (0, 0)][DBLP]
   IPPS/SPDP Workshops, 1998, pp:31-36 [Conf]
   
9. Iyad Ouaiss, Ranga Vemuri
   Global memory mapping for FPGA-based reconfigurable systems. [Citation Graph (0, 0)][DBLP]
   IPDPS, 2001, pp:144- [Conf]
   
10. 
    Deadline-based connection setup in wavelength-routed WDM networks. [Citation Graph (, )][DBLP]