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Ki-Seok Chung: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Taewhan Kim, Ki-Seok Chung, Chien-Liang Liu
    A Static Estimation Technique of Power Sensitivity in Logic Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:215-219 [Conf]
  2. Jaewon Seo, Taewhan Kim, Ki-Seok Chung
    Profile-based optimal intra-task voltage scheduling for hard real-time applications. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:87-92 [Conf]
  3. Taewhan Kim, Ki-Seok Chung, Chien-Liang Liu
    A Stepwise Refinement Data Path Synthesis Procedure for Easy Testability. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:586-590 [Conf]
  4. Ki-Seok Chung, Taewhan Kim, Chien-Liang Liu
    Behavioral-level partitioning for low power design in control-dominated application. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:156-161 [Conf]
  5. Ki-Seok Chung, Rajesh K. Gupta, C. L. Liu
    An algorithm for synthesis of system-level interface circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:442-447 [Conf]
  6. Unni Narayanan, Ki-Seok Chung, Taewhan Kim
    Enhanced bus invert encodings for low-power. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:25-28 [Conf]
  7. Ki-Seok Chung, C. L. Liu
    Local transformation techniques for multi-level logiccircuits utilizing circuit symmetries for power reduction. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:215-220 [Conf]
  8. Unni Narayanan, Hon Wai Leong, Ki-Seok Chung, Chien-Liang Liu
    Low power multiplexer decomposition. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1997, pp:269-274 [Conf]
  9. J. K. Kim, S. H. Won, Ki-Seok Chung, H. D. Cho, T. W. Kang, T. S. Nam, C. S. Kang, C. H. Yi, D. S. Kim
    Properties of A1/BaTa2O6/GaN MIS Structure. [Citation Graph (0, 0)][DBLP]
    VLSI, 2003, pp:240-243 [Conf]
  10. Sungpack Hong, Taewhan Kim, Unni Narayanan, Ki-Seok Chung
    Decomposition of Bus-Invert Coding for Low-Power I/O. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2000, v:10, n:1-2, pp:101-112 [Journal]
  11. Ki-Seok Chung, Taewhan Kim, C. L. Liu
    A Complete Model for Glitch Analysis in Logic Circuits. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2002, v:11, n:2, pp:137-154 [Journal]
  12. Young-Geun Lee, Joo-Yul Park, Ki-Seok Chung
    Design of Low Power MAC Operator with Dual Precision Mode. [Citation Graph (0, 0)][DBLP]
    RTCSA, 2007, pp:309-318 [Conf]

  13. Predictive power aware management for embedded mobile devices. [Citation Graph (, )][DBLP]

  14. Implementation of IEEE802.11a software defined receiver on chip multi-processor architecture using OpenMP. [Citation Graph (, )][DBLP]

  15. Performance evaluation of on-chip interconnect IP using CBR traffic generator model. [Citation Graph (, )][DBLP]

  16. A unified power measurement and management platform for pipelined MPSoC executions. [Citation Graph (, )][DBLP]

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