Search the dblp DataBase

Publications of Author

1. Ki-Wook Kim, Unni Narayanan, Sung-Mo Kang
   Domino logic synthesis minimizing crosstalk. [Citation Graph (0, 0)][DBLP]
   DAC, 2000, pp:280-285 [Conf]
   
2. Priyadarshan Patra, Unni Narayanan
   Automated Phase Assignment for the Synthesis of Low Power Domino Circuits. [Citation Graph (0, 0)][DBLP]
   DAC, 1999, pp:379-384 [Conf]
   
3. Unni Narayanan, C. L. Liu
   Low power logic synthesis for XOR based circuits. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1997, pp:570-574 [Conf]
   
4. Unni Narayanan, Ki-Seok Chung, Taewhan Kim
   Enhanced bus invert encodings for low-power. [Citation Graph (0, 0)][DBLP]
   ISCAS (5), 2002, pp:25-28 [Conf]
   
5. Ki-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L. Liu, Sung-Mo Kang
   Noise-aware power optimization for on-chip interconnect. [Citation Graph (0, 0)][DBLP]
   ISLPED, 2000, pp:108-113 [Conf]
   
6. Unni Narayanan, Hon Wai Leong, Ki-Seok Chung, Chien-Liang Liu
   Low power multiplexer decomposition. [Citation Graph (0, 0)][DBLP]
   ISLPED, 1997, pp:269-274 [Conf]
   
7. Unni Narayanan, Peichen Pan, C. L. Liu
   Low power logic synthesis under a general delay model. [Citation Graph (0, 0)][DBLP]
   ISLPED, 1998, pp:209-214 [Conf]
   
8. Unni Narayanan, Georgios I. Stamoulis, Rabindra K. Roy
   Characterizing Individual Gate Power Sensitivity in Low Power Design. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 1999, pp:625-0 [Conf]
   
9. Sungpack Hong, Taewhan Kim, Unni Narayanan, Ki-Seok Chung
   Decomposition of Bus-Invert Coding for Low-Power I/O. [Citation Graph (0, 0)][DBLP]
   Journal of Circuits, Systems, and Computers, 2000, v:10, n:1-2, pp:101-112 [Journal]
   
10. Ki-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L. Liu, Sung-Mo Kang
    Noise-aware interconnect power optimization in domino logic synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:1, pp:79-89 [Journal]