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Publications of Author

1. Jongman Kim, Dongkook Park, Theo Theocharides, Narayanan Vijaykrishnan, Chita R. Das
   A low latency router supporting adaptivity for on-chip interconnects. [Citation Graph (0, 0)][DBLP]
   DAC, 2005, pp:559-564 [Conf]
   
2. Dongkook Park, Chrysostomos Nicopoulos, Jongman Kim, Narayanan Vijaykrishnan, Chita R. Das
   Exploring Fault-Tolerant Network-on-Chip Architectures. [Citation Graph (0, 0)][DBLP]
   DSN, 2006, pp:93-104 [Conf]
   
3. Jongman Kim, Chrysostomos Nicopoulos, Dongkook Park
   A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks. [Citation Graph (0, 0)][DBLP]
   ISCA, 2006, pp:4-15 [Conf]
   
4. Chrysostomos Nicopoulos, Dongkook Park, Jongman Kim, Narayanan Vijaykrishnan, Mazin S. Yousif, Chita R. Das
   ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers. [Citation Graph (0, 0)][DBLP]
   MICRO, 2006, pp:333-346 [Conf]
   
5. Thomas D. Richardson, Chrysostomos Nicopoulos, Dongkook Park, Narayanan Vijaykrishnan, Yuan Xie, Chita R. Das, Vijay Degalahal
   A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2006, pp:657-664 [Conf]
   
6. Jongman Kim, Dongkook Park, Chrysostomos Nicopoulos, Narayanan Vijaykrishnan, Chita R. Das
   Design and analysis of an NoC architecture from performance, reliability and energy perspective. [Citation Graph (0, 0)][DBLP]
   ANCS, 2005, pp:173-182 [Conf]
   
7. Jongman Kim, Chrysostomos Nicopoulos, Dongkook Park, Reetuparna Das, Yuan Xie, Narayanan Vijaykrishnan, Mazin S. Yousif, Chita R. Das
   A novel dimensionally-decomposed router for on-chip communication in 3D architectures. [Citation Graph (0, 0)][DBLP]
   ISCA, 2007, pp:138-149 [Conf]
   
8. 
   FPGA-based prototyping of a 2D MESH / TORUS on-chip interconnect (abstract only). [Citation Graph (, )][DBLP]
   
   
9. 
   Performance and power optimization through data compression in Network-on-Chip architectures. [Citation Graph (, )][DBLP]
   
   
10. 
    MIRA: A Multi-layered On-Chip Interconnect Router Architecture. [Citation Graph (, )][DBLP]