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Publications of Author

1. Fatih Kocan, Daniel G. Saab
   Dynamic Fault Diagnosis on Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
   DAC, 1999, pp:691-696 [Conf]
   
2. Alex Fit-Florea, Miroslav Halas, Fatih Kocan
   Enhancing Reliability of Operational Interconnections in FPGAs. [Citation Graph (0, 0)][DBLP]
   DATE, 2004, pp:746-747 [Conf]
   
3. Fatih Kocan
   Reconfigurable Randomized K-way Graph Partitioning. [Citation Graph (0, 0)][DBLP]
   DSD, 2003, pp:272-278 [Conf]
   
4. Fatih Kocan
   Reconfigurable randomized K-way graph partitioning. [Citation Graph (0, 0)][DBLP]
   FPGA, 2003, pp:245- [Conf]
   
5. Fatih Kocan, Jason Meyer
   Logic Modules with Shared SRAM Tables for Field-Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP]
   FPL, 2004, pp:289-300 [Conf]
   
6. Daniel G. Saab, Fatih Kocan, Jacob A. Abraham
   Massively Parallel/Reconfigurable Emulation Model for the D-algorithm. [Citation Graph (0, 0)][DBLP]
   FPL, 2002, pp:1172-1176 [Conf]
   
7. Fatih Kocan, Daniel G. Saab
   Concurrent D-algorithm on reconfigurable hardware. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1999, pp:152-156 [Conf]
   
8. Fatih Kocan, Mehmet Hadi Gunes
   On the ZBDD-based nonenumerative path delay fault coverage calculation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:7, pp:1137-1143 [Journal]
   
9. Fatih Kocan, Mehmet Hadi Gunes
   Acyclic circuit partitioning for path delay fault emulation. [Citation Graph (0, 0)][DBLP]
   AICCSA, 2005, pp:22- [Conf]
   
10. Jason Meyer, Fatih Kocan
    Sharing of SRAM Tables Among NPN-Equivalent LUTs in SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:2, pp:182-195 [Journal]
    
11. Fatih Kocan, Daniel G. Saab
    ATPG for combinational circuits on configurable hardware. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:1, pp:117-129 [Journal]
    
12. Fatih Kocan, Daniel G. Saab
    Correction to "ATPG for combinational circuits on configurable hardware". [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:3, pp:374-374 [Journal]
    
13. 
    Critical Path Delay Reduction in FPGAs with Unbalanced Lookup Times. [Citation Graph (, )][DBLP]