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Haluk Konuk: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Haluk Konuk, F. Joel Ferguson, Tracy Larrabee
    Accurate and Efficient Fault Simulation of Realistic CMOS Network Breaks. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:345-351 [Conf]
  2. Christos A. Papachristou, Haluk Konuk
    A Linear Program Driven Scheduling and Allocation Method Followed by an Interconnect Optimization Algorithm. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:77-83 [Conf]
  3. Haluk Konuk
    Fault simulation of interconnect opens in digital CMOS circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:548-554 [Conf]
  4. Haluk Konuk
    On invalidation mechanisms for non-robust delay tests. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:393-399 [Conf]
  5. Haluk Konuk, F. Joel Ferguson
    Oscillation and Sequential Behavior Caused by Interconnect Opens in Digital CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:597-606 [Conf]
  6. Haluk Konuk, Leon Xiao
    DFFT : Design For Functional Testability. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:1105-1114 [Conf]
  7. Bill Underwood, Wai-on Law, Sungho Kang, Haluk Konuk
    Fastpath: A Path-Delay Test Generator for Standard Scan Designs. [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:154-163 [Conf]
  8. C.-H. Chia, Sujit Dey, Faraydon Karim, Haluk Konuk, Keesup Kim
    Validation and Test of Network Processors and ASICs. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:407-410 [Conf]
  9. Haluk Konuk, F. Joel Ferguson
    An unexpected factor in testing for CMOS opens: the die surface. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:422-429 [Conf]
  10. Haluk Konuk
    Voltage- and current-based fault simulation for interconnect open defects. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:12, pp:1768-1779 [Journal]
  11. Haluk Konuk, F. Joel Ferguson
    Oscillation and sequential behavior caused by opens in the routing in digital CMOS circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:11, pp:1200-1210 [Journal]
  12. Haluk Konuk, F. Joel Ferguson, Tracy Larrabee
    Charge-based fault simulation for CMOS network breaks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:12, pp:1555-1567 [Journal]

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