The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

F. Joel Ferguson: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Haluk Konuk, F. Joel Ferguson, Tracy Larrabee
    Accurate and Efficient Fault Simulation of Realistic CMOS Network Breaks. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:345-351 [Conf]
  2. Sezer Gören, F. Joel Ferguson
    CHESMIN: A Heuristic for State Reduction in Incompletely Specified Finite State Machines. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:248-254 [Conf]
  3. Richard McGowen, F. Joel Ferguson
    A Study of Undetectable Non-Feedback Shorts for the Purpose of Physical-DFT. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:371-375 [Conf]
  4. Shalini Ghosh, F. Joel Ferguson
    Estimating detection probability of interconnect opens using stuck-at tests. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:254-259 [Conf]
  5. Brian Chess, David B. Lavo, F. Joel Ferguson, Tracy Larrabee
    Diagnosis of realistic bridging faults with single stuck-at information. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:185-192 [Conf]
  6. Brian Chess, Anthony Freitas, F. Joel Ferguson, Tracy Larrabee
    Testing CMOS Logic Gates for Realistic Shorts. [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:395-402 [Conf]
  7. F. Joel Ferguson, Tracy Larrabee
    Test Pattern Generation for Realistic Bridge Faults in CMOS ICs. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:492-499 [Conf]
  8. Sezer Gören, F. Joel Ferguson
    Testing Finite State Machines Based on a Structural Coverage Metric . [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:773-780 [Conf]
  9. Sezer Gören, F. Joel Ferguson
    Checking sequence generation for asynchronous sequential elements. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:406-413 [Conf]
  10. Charles F. Hawkins, Jerry M. Soden, Alan W. Righter, F. Joel Ferguson
    Defect Classes - An Overdue Paradigm for CMOS IC. [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:413-425 [Conf]
  11. Haluk Konuk, F. Joel Ferguson
    Oscillation and Sequential Behavior Caused by Interconnect Opens in Digital CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:597-606 [Conf]
  12. David B. Lavo, Tracy Larrabee, F. Joel Ferguson, Brian Chess, Jayashree Saxena, Kenneth M. Butler
    Bridging Fault Diagnosis in the Absence of Physical Information. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:887-893 [Conf]
  13. Wojciech Maly, F. Joel Ferguson, John Paul Shen
    Systematic Characterization of Physical Defects for Fault Analysis of MOS IC Cells. [Citation Graph (0, 0)][DBLP]
    ITC, 1984, pp:390-399 [Conf]
  14. Richard McGowen, F. Joel Ferguson
    Incorporating Physical Design-for-Test into Routing. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:685-693 [Conf]
  15. Jayashree Saxena, Kenneth M. Butler, Hari Balachandran, David B. Lavo, Tracy Larrabee, F. Joel Ferguson, Brian Chess
    On applying non-classical defect models to automated diagnosis. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:748-757 [Conf]
  16. John Paul Shen, F. Joel Ferguson
    Extraction and Simulation of Realistic CMOS Faults Using Inductive Fault Analysis. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:475-484 [Conf]
  17. Haluk Konuk, F. Joel Ferguson
    An unexpected factor in testing for CMOS opens: the die surface. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:422-429 [Conf]
  18. A. Jee, F. Joel Ferguson
    A methodolgy for characterizing cell testability. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:384-390 [Conf]
  19. Michael A. Margolese, F. Joel Ferguson
    Using Temporal Constraints for Eliminating Crosstalk Candidates for Design and Test. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:80-85 [Conf]
  20. Douglas Williams, F. Joel Ferguson, Tracy Larrabee
    A Study on the Utility of Using Expected Quality Level as a Design for Testability Metric. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:274-282 [Conf]
  21. Jingjing Xu, Rahul Kundu, F. Joel Ferguson
    A Systematic DFT Procedure for Library Cells. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:460-466 [Conf]
  22. Shalini Ghosh, F. Joel Ferguson
    Detection probabilities of interconnect breaks: an analysis. [Citation Graph (0, 0)][DBLP]
    Integration, 2005, v:38, n:3, pp:451-465 [Journal]
  23. Martine D. F. Schlag, F. Joel Ferguson
    Detection of Multiple Faults in Two-Dimensional ILAs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:6, pp:741-746 [Journal]
  24. John Paul Shen, F. Joel Ferguson
    The Design of Easily Tastabel VLSI Array Multipliers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1984, v:33, n:6, pp:554-560 [Journal]
  25. F. Joel Ferguson
    Detection of multiple faults in MOS circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:9, pp:1009-1014 [Journal]
  26. F. Joel Ferguson, John Paul Shen
    A CMOS fault extractor for inductive fault analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:11, pp:1181-1194 [Journal]
  27. Haluk Konuk, F. Joel Ferguson
    Oscillation and sequential behavior caused by opens in the routing in digital CMOS circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:11, pp:1200-1210 [Journal]
  28. Haluk Konuk, F. Joel Ferguson, Tracy Larrabee
    Charge-based fault simulation for CMOS network breaks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:12, pp:1555-1567 [Journal]
  29. David B. Lavo, Brian Chess, Tracy Larrabee, F. Joel Ferguson
    Diagnosing realistic bridging faults with single stuck-at information. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:3, pp:255-268 [Journal]
  30. Sezer Gören, F. Joel Ferguson
    Test sequence generation for controller verification and test with high coverage. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:4, pp:916-938 [Journal]
  31. Sezer Gören, F. Joel Ferguson
    On state reduction of incompletely specified finite state machines. [Citation Graph (0, 0)][DBLP]
    Computers & Electrical Engineering, 2007, v:33, n:1, pp:58-69 [Journal]

Search in 0.003secs, Finished in 0.005secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002