Donald E. Thomas, John A. Nestor Defining and Implementing a Multilevel Design Representation with Simulation Applications. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1983, v:2, n:3, pp:135-145 [Journal]
John A. Nestor L3: An FPGA-based multilayer maze routing accelerator. [Citation Graph (0, 0)][DBLP] Microprocessors and Microsystems, 2005, v:29, n:2-3, pp:87-97 [Journal]
John A. Nestor Visual register-transfer description of VLSI microarchitectures. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 1993, v:1, n:1, pp:72-76 [Journal]
L4: An FPGA-Based Accelerator for Detailed Maze Routing. [Citation Graph (, )][DBLP]
VCache: visualization applet for processor caches. [Citation Graph (, )][DBLP]
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