The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

John A. Nestor: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ganesh Krishnamoorthy, John A. Nestor
    Data Path Allocation using an Extended Binding Model. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:279-284 [Conf]
  2. Donald E. Thomas, Elizabeth M. Dirkes, Robert A. Walker, Jayanth V. Rajan, John A. Nestor, Robert L. Blackburn
    The System Architect's Workbench. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:337-343 [Conf]
  3. John A. Nestor
    FPGA Implementation of a Maze Routing Accelerator. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:992-995 [Conf]
  4. John A. Nestor
    A new look at hardware maze routing. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2002, pp:142-147 [Conf]
  5. John A. Nestor, Ganesh Krishnamoorthy
    SALSA: A New Approach to Scheduling with Timing Constraints. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:262-265 [Conf]
  6. Michael R. Rhinehart, John A. Nestor
    SALSE II: A Fast Transformational Scheduler for High-level Synthesis. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1678-1681 [Conf]
  7. John A. Nestor, Bassel Soudan, Zubair Mayet
    MIES: a microarchitecture design tool. [Citation Graph (0, 0)][DBLP]
    MICRO, 1989, pp:217-222 [Conf]
  8. John A. Nestor, David A. Rich
    Integrating Digital, Analog, and Mixed-Signal Design in an Undergraduate ECE Curriculum. [Citation Graph (0, 0)][DBLP]
    MSE, 2003, pp:89-90 [Conf]
  9. John A. Nestor
    Web-Based Visualization Tools for Teaching VLSI CAD Algorithms. [Citation Graph (0, 0)][DBLP]
    MSE, 2001, pp:100-101 [Conf]
  10. John A. Nestor
    Teaching Computer Organization with HDLs: An Incremental Approach. [Citation Graph (0, 0)][DBLP]
    MSE, 2005, pp:77-78 [Conf]
  11. John A. Nestor, Ganesh Krishnamoorthy
    SALSA: a new approach to scheduling with timing constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:8, pp:1107-1122 [Journal]
  12. Donald E. Thomas, John A. Nestor
    Defining and Implementing a Multilevel Design Representation with Simulation Applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1983, v:2, n:3, pp:135-145 [Journal]
  13. John A. Nestor
    L3: An FPGA-based multilayer maze routing accelerator. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2005, v:29, n:2-3, pp:87-97 [Journal]
  14. John A. Nestor
    Visual register-transfer description of VLSI microarchitectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:1, pp:72-76 [Journal]

  15. L4: An FPGA-Based Accelerator for Detailed Maze Routing. [Citation Graph (, )][DBLP]


  16. VCache: visualization applet for processor caches. [Citation Graph (, )][DBLP]


Search in 0.004secs, Finished in 0.005secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002