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Helena Krupnova: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Helena Krupnova, Ali Abbara, Gabriele Saucier
    A Hierarchy-Driven FPGA Partitioning Method. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:522-525 [Conf]
  2. Helena Krupnova
    Mapping Multi-Million Gate SoCs on FPGAs: Industrial Methodology and Experience. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1236-1243 [Conf]
  3. Helena Krupnova, Gabriele Saucier
    Iterative Improvement Based Multi-Way Netlist Partitioning for FPGAs. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:587-0 [Conf]
  4. Helena Krupnova, B. Behnam, Gabriele Saucier
    Block and IP Wrapping for Efficient Design on FPGAs (Abstract). [Citation Graph (0, 0)][DBLP]
    FPGA, 1998, pp:256- [Conf]
  5. Helena Krupnova, Christian Rabedaoro, Gabriele Saucier
    Synthesis and Floorplanning for Large Hierarchical FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 1997, pp:105-111 [Conf]
  6. Helena Krupnova, Gabriele Saucier
    Partitioning Large Designs by Filling PFGA Devices with Hierarchy Blocks. [Citation Graph (0, 0)][DBLP]
    FPGA, 1999, pp:251- [Conf]
  7. S. A. Senouci, A. Amoura, Helena Krupnova, Gabriele Saucier
    Timing Driven Floorplanning on Programmable Hierarchical Targets. [Citation Graph (0, 0)][DBLP]
    FPGA, 1998, pp:85-92 [Conf]
  8. A. Bigot, F. Charpentier, Helena Krupnova, I. Sans
    Deploying Hardware Platforms for SoC Validation: An Industrial Case Study. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:64-73 [Conf]
  9. Helena Krupnova, Vu DucAnh Dinh, Gabriele Saucier
    A Knowledge-Based System for Prototyping on FPFAs. [Citation Graph (0, 0)][DBLP]
    FPL, 1998, pp:89-98 [Conf]
  10. Helena Krupnova, Veronique Meurou, Christophe Barnichon, Carlos Serra, Farid Morsi
    How Fast Is Rapid FPGA-based Prototyping: Lessons and Challenges from the Digital TV Design Prototyping Project. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:26-35 [Conf]
  11. Helena Krupnova, Gabriele Saucier
    FPGA-Based Emulation: Industrial and Custom Prototyping Solutions. [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:68-77 [Conf]
  12. Helena Krupnova, Gabriele Saucier
    Hierarchical Interactive Approach to Partition Large Designs into FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 1999, pp:101-110 [Conf]
  13. Helena Krupnova, Christian Rabedaoro, Gabriele Saucier
    FPGA Partitioning for Rapid Prototyping: A 1 Million Gate Design Case Study. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 1999, pp:128-133 [Conf]
  14. Helena Krupnova, Gabriele Saucier
    FPGA Technology Snapshot: Current Devices and Design Tools. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2000, pp:200-0 [Conf]
  15. Helena Krupnova, D. D. A. Vu, Gabriele Saucier, M. Boubal
    Real Time Prototyping Method and a Case Study. [Citation Graph (0, 0)][DBLP]
    International Workshop on Rapid System Prototyping, 1998, pp:13-18 [Conf]

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