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Publications of Author

1. Byunggyu Kwak, Eun Sei Park
   An Optimization-Based Error Calculation for Statistical Power Estimation of CMOS Logic Circuits. [Citation Graph (0, 0)][DBLP]
   DAC, 1998, pp:690-693 [Conf]
   
2. Eun Sei Park, M. Ray Mercer
   An Efficient Delay Test Generation System for Combinational Logic Circuits. [Citation Graph (0, 0)][DBLP]
   DAC, 1990, pp:522-528 [Conf]
   
3. Sung Tae Jung, Eun Sei Park, Jung Sik Kim, Chu Shik Jhon
   Automatic Synthesis of Gate-Level Speed-Independent Control Circuits from Signal Transition Graphs. [Citation Graph (0, 0)][DBLP]
   ISCAS, 1995, pp:1211-1214 [Conf]
   
4. Eun Sei Park, M. Ray Mercer
   Switch-Level ATPG Using Constraint-Guided Line Justification. [Citation Graph (0, 0)][DBLP]
   ITC, 1993, pp:616-625 [Conf]
   
5. Eun Sei Park, Bill Underwood, Thomas W. Williams, M. Ray Mercer
   Delay Testing Quality in Timing-Optimized Designs. [Citation Graph (0, 0)][DBLP]
   ITC, 1991, pp:897-905 [Conf]
   
6. Eun Sei Park, Thomas W. Williams, M. Ray Mercer
   Statistical Delay Fault Coverage and Defect Level for Delay Faults. [Citation Graph (0, 0)][DBLP]
   ITC, 1988, pp:492-499 [Conf]
   
7. Eun Sei Park, M. Ray Mercer, Thomas W. Williams
   The Total Delay Fault Model and Statistical Delay Fault Coverage. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1992, v:41, n:6, pp:688-698 [Journal]
   
8. Eun Sei Park, M. Ray Mercer
   An efficient delay test generation system for combinational logic circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:7, pp:926-938 [Journal]