The SCEAS System
Navigation Menu

Search the dblp DataBase


David E. Lackey: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. David E. Lackey, Paul S. Zuchowski, Jürgen Koehl
    Designing mega-ASICs in nanogate technologies. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:770-775 [Conf]
  2. David E. Lackey, Paul S. Zuchowski, Thomas R. Bednar, Douglas W. Stout, Scott W. Gould, John M. Cohn
    Managing power and performance for System-on-Chip designs using Voltage Islands. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:195-202 [Conf]
  3. Vikram Iyengar, Kenneth Pichamuthu, Andrew Ferko, Frank Woytowich, David E. Lackey, Gary Grise, Mark Taylor, Mike Degregorio, Steven F. Oakland
    An Integrated Framework for At-Speed and ATE-Driven Delay Test of Contract-Manufactured ASICs. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:173-178 [Conf]
  4. George W. Doerre, David E. Lackey
    The IBM ASIC/SoC methodology - A recipe for first-time success. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 2002, v:46, n:6, pp:649-660 [Journal]

  5. Variation-aware performance verification using at-speed structural test and statistical timing. [Citation Graph (, )][DBLP]

Search in 0.002secs, Finished in 0.003secs
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002