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Publications of Author

1. David E. Lackey, Paul S. Zuchowski, Jürgen Koehl
   Designing mega-ASICs in nanogate technologies. [Citation Graph (0, 0)][DBLP]
   DAC, 2003, pp:770-775 [Conf]
   
2. Ren-Song Tsay, Jürgen Koehl
   An Analytic Net Weighting Approach for Performance Optimization in Circuit Placement. [Citation Graph (0, 0)][DBLP]
   DAC, 1991, pp:620-625 [Conf]
   
3. Markus Bühler, Jürgen Koehl, Jeanne Bickford, Jason Hibbeler, Ulf Schlichtmann, R. Sommer, Michael Pronath, A. Ripp
   DFM/DFY design for manufacturability and yield - influence of process variations in digital, analog and mixed-signal circuit design. [Citation Graph (0, 0)][DBLP]
   DATE, 2006, pp:387-392 [Conf]
   
4. Jürgen Koehl, Ulrich Baur, Thomas Ludwig, Bernhard Kick, Thomas Pflueger
   A Flat, Timing-Driven Design System for a High-Performance CMOS Processor Chipset. [Citation Graph (0, 0)][DBLP]
   DATE, 1998, pp:312-320 [Conf]
   
5. Philipp V. Panitz, Markus Olbrich, Erich Barke, Jürgen Koehl
   Robust wiring networks for DfY considering timing constraints. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2007, pp:43-48 [Conf]
   
6. Rob A. Rutenbar, Olivier Coudert, Patrick Groeneveld, Jürgen Koehl, Scott Peterson, Vivek Raghavan, Naresh Soni
   Automatic Hierarchical Design: Fantasy or Reality? (Panel). [Citation Graph (0, 0)][DBLP]
   ICCAD, 2001, pp:656-0 [Conf]
   
7. Tilmann Stöhr, Markus Alt, Asmus Hetzel, Jürgen Koehl
   Analysis, reduction and avoidance of crosstalk on VLSI chips. [Citation Graph (0, 0)][DBLP]
   ISPD, 1998, pp:211-218 [Conf]
   
8. Jeanne Bickford, Jason Hibbeler, Markus Bühler, Jürgen Koehl, Dirk Muller, Sven Peyer, Christian Schulte
   Yield Improvement by Local Wiring Redundancy. [Citation Graph (0, 0)][DBLP]
   ISQED, 2006, pp:473-478 [Conf]
   
9. 
   Considering possible opens in non-tree topology wire delay calculation. [Citation Graph (, )][DBLP]