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Charles Njinda:
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- Kuen-Jong Lee, Charles Njinda, Melvin A. Breuer
SWiTEST: A Switch Level Test Generation System for CMOS Combinational Circuits. [Citation Graph (0, 0)][DBLP] DAC, 1992, pp:26-29 [Conf]
- Ishwar Parulkar, Melvin A. Breuer, Charles Njinda
Extraction of a High-level structural Representation from Circuit Descriptions with Applications to DFT/BIST. [Citation Graph (0, 0)][DBLP] DAC, 1994, pp:345-356 [Conf]
- Rajesh Raina, Robert Bailey, Charles Njinda, Robert F. Molyneaux, Charlie Beh
Efficient Testing of Clock Regenerator Circuits in Scan Designs. [Citation Graph (0, 0)][DBLP] DAC, 1997, pp:95-100 [Conf]
- Sen-Pin Lin, Charles Njinda, Melvin A. Breuer
A Systematic Approach for Designing Testable VLSI Circuits. [Citation Graph (0, 0)][DBLP] ICCAD, 1991, pp:496-499 [Conf]
- Debaditya Mukherjee, Charles Njinda, Melvin A. Breuer
Synthesis of Optimal 1-Hot Coded On-Chip Controllers for BIST Hardware. [Citation Graph (0, 0)][DBLP] ICCAD, 1991, pp:236-239 [Conf]
- Sridhar Narayanan, Charles Njinda, Melvin A. Breuer
Optimal Sequencing of Scan Registers. [Citation Graph (0, 0)][DBLP] ITC, 1992, pp:293-302 [Conf]
- Charles Njinda
A Hierarchical DFT Architecture for Chip, Board and System Test/Debug. [Citation Graph (0, 0)][DBLP] ITC, 2004, pp:1061-1071 [Conf]
- Charles Njinda, Neeraj Kaul
Performance Driven BIST Technique for Random Logic. [Citation Graph (0, 0)][DBLP] ITC, 1995, pp:524-533 [Conf]
- Rajesh Raina, Charles Njinda, Robert F. Molyneaux
How Seriously Do You Take Your Possible-Detect Faults? [Citation Graph (0, 0)][DBLP] ITC, 1997, pp:819-828 [Conf]
- Kuen-Jong Lee, Charles Njinda, Melvin A. Breuer
SWiTEST: a switch level test generation system for CMOS combinational circuits. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:5, pp:625-637 [Journal]
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