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Jaushin Lee: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jaushin Lee, Janak H. Patel
    Hierarchical Test Generation under Intensive Global Functional Constraints. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:261-266 [Conf]
  2. Jaushin Lee, Janak H. Patel
    An Architectural Level Test Generator for a Hierarchical Design Environment. [Citation Graph (0, 0)][DBLP]
    FTCS, 1991, pp:44-51 [Conf]
  3. Vivek Chickermane, Jaushin Lee, Janak H. Patel
    A comparative study of design for testability methods using high-level and gate-level descriptions. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:620-624 [Conf]
  4. Jaushin Lee, Janak H. Patel
    A Signal-Driven Discrete Relaxation Technique for Architectural Level Test Generation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:458-461 [Conf]
  5. Vivek Chickermane, Jaushin Lee, Janak H. Patel
    Design for Testability Using Architectural Descriptions. [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:752-761 [Conf]
  6. Jaushin Lee, Janak H. Patel
    ARTEST: An Architectural Level Test Generator for Data Path Faults and Control Faults. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:729-738 [Conf]
  7. Jaushin Lee, Janak H. Patel
    An Instruction Sequence Assembling Methodology for Testing Microprocessors. [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:49-58 [Conf]
  8. Vivek Chickermane, Jaushin Lee, Janak H. Patel
    Addressing design for testability at the architectural level. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:7, pp:920-934 [Journal]
  9. Jaushin Lee, Janak H. Patel
    Architectural level test generation for microprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:10, pp:1288-1300 [Journal]
  10. Jaushin Lee, Janak H. Patel
    Hierarchical test generation under architectural level functional constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:9, pp:1144-1151 [Journal]

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