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Régis Leveugle: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Régis Leveugle
    Optimized State Assignment of single fault Tolerant FSMs Based on SEC Codes. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:14-18 [Conf]
  2. Yannick Monnet, Marc Renaudin, Régis Leveugle
    Asynchronous circuits transient faults sensitivity evaluation. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:863-868 [Conf]
  3. Régis Leveugle
    Automatic Modifications of High Level VHDL Descriptions for Fault Detection or Tolerance. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:837-841 [Conf]
  4. Régis Leveugle, Abdelaziz Ammari
    Early SEU Fault Injection in Digital, Analog and Mixed Signal Circuits: A Global Flow. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:590-595 [Conf]
  5. Régis Leveugle, V. Maingot
    On the Use of Information Redundancy When Designing Secure Chips. [Citation Graph (0, 0)][DBLP]
    DDECS, 2006, pp:141-142 [Conf]
  6. Pierre Vanhauwaert, Régis Leveugle, Philippe Roche
    A Flexible SoPC-based Fault Injection Environment. [Citation Graph (0, 0)][DBLP]
    DDECS, 2006, pp:192-197 [Conf]
  7. Abdelaziz Ammari, Régis Leveugle, B. Nicolescu, Yvon Savaria
    Evaluation of a Software-Based Error Detection Technique by RT-Level Fault Injection. [Citation Graph (0, 0)][DBLP]
    DELTA, 2006, pp:488-493 [Conf]
  8. Abdelaziz Ammari, Régis Leveugle, Matteo Sonza Reorda, Massimo Violante
    Detailed Comparison of Dependability Analyses Performed at RT and Gate Levels. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:336-343 [Conf]
  9. Lörinc Antoni, Régis Leveugle, Béla Fehér
    Using Run-Time Reconfiguration for Fault Injection in Hardware Prototypes. [Citation Graph (0, 0)][DBLP]
    DFT, 2000, pp:405-413 [Conf]
  10. Lörinc Antoni, Régis Leveugle, Béla Fehér
    Using Run-Time Reconfiguration for Fault Injection in Hardware Prototypes. [Citation Graph (0, 0)][DBLP]
    DFT, 2002, pp:245-253 [Conf]
  11. Régis Leveugle
    Fault Injection in VHDL Descriptions and Emulation. [Citation Graph (0, 0)][DBLP]
    DFT, 2000, pp:414-0 [Conf]
  12. Régis Leveugle
    A Low-Cost Hardware Approach to Dependability Validation of Ips. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:242-249 [Conf]
  13. Régis Leveugle, R. Cercueil
    High Level Modifications of VHDL Descriptions for On-Line Test or Fault Tolerance. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:84-0 [Conf]
  14. Régis Leveugle, D. Cimonnet, Abdelaziz Ammari
    System-Level Dependability Analysis with RT-Level Fault Injection Accuracy. [Citation Graph (0, 0)][DBLP]
    DFT, 2004, pp:451-458 [Conf]
  15. Régis Leveugle, R. Rochet, Gabriele Saucier
    Alternative Approaches to Fault Detection in FSMs. [Citation Graph (0, 0)][DBLP]
    DFT, 1994, pp:271-279 [Conf]
  16. R. Rochet, Régis Leveugle, Gabriele Saucier
    Analysis and Comparison of Fault Tolerant FSM Architectures Based on SEC Codes. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:9-16 [Conf]
  17. Raoul Velazco, Régis Leveugle, O. Calvo
    Upset-Like Fault Injection in VHDL Descriptions: A Method and Preliminary Results. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:259-0 [Conf]
  18. X. Wendling, H. Chauvet, Lionel Revéret, R. Rochet, Régis Leveugle
    Automatic and Optimized Synthesis of Dataparts with Fault Detection or Tolerance Capabilities. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:195-203 [Conf]
  19. Michele Portolan, Régis Leveugle
    Towards a Secure and Reliable System. [Citation Graph (0, 0)][DBLP]
    EUC, 2005, pp:1085-1098 [Conf]
  20. T. Michel, Régis Leveugle, Gabriele Saucier, R. Doucet, P. Chapier
    Taking Advantage of ASICs to Improve Dependability with Very Low Overheads. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:14-18 [Conf]
  21. C. Safinia, Régis Leveugle, Gabriele Saucier
    Taking Advantage of High Level Functional Information to Refine Timing Analysis and Timing Modeling. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:349-353 [Conf]
  22. Yannick Monnet, Marc Renaudin, Régis Leveugle, Christophe Clavier, Pascal Moitrel
    Case Study of a Fault Attack on Asynchronous DES Crypto-Processors. [Citation Graph (0, 0)][DBLP]
    FDTC, 2006, pp:88-97 [Conf]
  23. Régis Leveugle, R. Rochet, Gabriele Saucier, L. Martinez, C. Pitot
    A Synthesis Tool for Fault-Tolerant Finite State Machines. [Citation Graph (0, 0)][DBLP]
    FTCS, 1993, pp:502-511 [Conf]
  24. T. Michel, Régis Leveugle, Gabriele Saucier
    A New Approach to Control Flow Checking Without Program Modification. [Citation Graph (0, 0)][DBLP]
    FTCS, 1991, pp:334-343 [Conf]
  25. Régis Leveugle, X. Delord, Gabriele Saucier
    Influence of Error Correlations on the Signature Analysis Aliasing. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:584-587 [Conf]
  26. Pierre Abouzeid, Régis Leveugle, Gabriele Saucier
    Logic Synthesis for Automatic Layout. [Citation Graph (0, 0)][DBLP]
    Synthesis for Control Dominated Circuits, 1992, pp:335-343 [Conf]
  27. L. Gerbaux, Régis Leveugle, Gabriele Saucier
    Synthesis of large controllers using ROM or PLA generators. [Citation Graph (0, 0)][DBLP]
    Synthesis for Control Dominated Circuits, 1992, pp:47-59 [Conf]
  28. Régis Leveugle, C. Safina
    Generation of optimized datapaths: bit-slice versus standard cells. [Citation Graph (0, 0)][DBLP]
    Synthesis for Control Dominated Circuits, 1992, pp:153-166 [Conf]
  29. C. Safina, Régis Leveugle
    Clocking scheme selection for circuits made up of a controller and a datapath. [Citation Graph (0, 0)][DBLP]
    Synthesis for Control Dominated Circuits, 1992, pp:293-308 [Conf]
  30. Yannick Monnet, Marc Renaudin, Régis Leveugle
    Asynchronous Circuits Sensitivity to Fault Injection. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:121-128 [Conf]
  31. Abdelaziz Ammari, K. Hadjiat, Régis Leveugle
    On Combining Fault Classification and Error Propagation Analysis in RT-Level Dependability Evaluation. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:227-232 [Conf]
  32. Régis Leveugle, K. Hadjiat
    Multi-Level Fault Injection Experiments Based on VHDL Descriptions: A Case Study. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2002, pp:107-111 [Conf]
  33. Michele Portolan, Régis Leveugle
    Operating System Function Reuse to Achieve Low-Cost Fault Tolerance. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:167-174 [Conf]
  34. Régis Leveugle, Yervant Zorian, Luca Breveglieri, André K. Nieuwland, Klaus Rothbart, Jean-Pierre Seifert
    On-Line Testing for Secure Implementations: Design and Validation. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:211- [Conf]
  35. Michele Portolan, Régis Leveugle
    On the Need for Common Evaluation Methods for Fault Tolerance Costs in Microprocessors. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:247-252 [Conf]
  36. Lorena Anghel, Régis Leveugle, Pierre Vanhauwaert
    Evaluation of SET and SEU Effects at Multiple Abstraction Levels. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:309-312 [Conf]
  37. Régis Leveugle
    Introduction to the Special Session on Secure Implementations. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:115- [Conf]
  38. Régis Leveugle
    A New Approach for Early Dependability Evaluation Based on Formal Property Checking and Controlled Mutations. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:260-265 [Conf]
  39. Yannick Monnet, Marc Renaudin, Régis Leveugle
    Hardening Techniques against Transient Faults for Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:129-134 [Conf]
  40. Yannick Monnet, Marc Renaudin, Régis Leveugle, Nathalie Feyt, Pascal Moitrel, F. M'Buwa Nzenguet
    Practical Evaluation of Fault Countermeasures on an Asynchronous DES Crypto Processor. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2006, pp:125-130 [Conf]
  41. Régis Leveugle, Lörinc Antoni, Béla Fehér
    Dependability Analysis: A New Application for Run-Time Reconfiguration. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:173- [Conf]
  42. M. Karam, Régis Leveugle, Gabriele Saucier
    Hierarchical Test Generation Based on Delayed Propagation. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:739-747 [Conf]
  43. Régis Leveugle, Gabriele Saucier
    Optimized Synthesis of Dedicated Controllers with Concurrent Checking Capabilities. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:355-363 [Conf]
  44. Alejandro Chagoya, Régis Leveugle
    Experiments on Multimedia Support of VLSI Design teaching in the MODEM Project. [Citation Graph (0, 0)][DBLP]
    MSE, 1999, pp:82-83 [Conf]
  45. Régis Leveugle
    Test of single fault tolerant controllers in VLSI circuits. [Citation Graph (0, 0)][DBLP]
    VLSI, 1993, pp:123-132 [Conf]
  46. X. Wendling, R. Rochet, Régis Leveugle
    Standard and ROM-based synthesis of FSMs with control flow checking capabilities. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:81-86 [Conf]
  47. Régis Leveugle, Zahava Koren, Israel Koren, Gabriele Saucier, Norbert Wehn
    The Hyeti Defect Tolerant Microprocessor: A Practical Experiment and its Cost-Effectiveness Analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:12, pp:1398-1406 [Journal]
  48. Régis Leveugle, Gabriele Saucier
    Optimized Synthesis of Concurrently Checked Controllers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:4, pp:419-425 [Journal]
  49. Yannick Monnet, Marc Renaudin, Régis Leveugle
    Designing Resistant Circuits against Malicious Faults Injection Using Asynchronous Logic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:9, pp:1104-1115 [Journal]
  50. Régis Leveugle, Abdelaziz Ammari, V. Maingot, E. Teyssou, Pascal Moitrel, Christophe Mourtel, Nathalie Feyt, Jean-Baptiste Rigaud, Assia Tria
    Experimental evaluation of protections against laser-induced faults and consequences on fault modeling. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1587-1592 [Conf]
  51. Yannick Monnet, Marc Renaudin, Régis Leveugle
    Formal Analysis of Quasi Delay Insensitive Circuits Behavior in the Presence of SEUs. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2007, pp:113-120 [Conf]
  52. Pierre Vanhauwaert, Régis Leveugle, Philippe Roche
    Reduced Instrumentation and Optimized Fault Injection Control for Dependability Analysis. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:391-396 [Conf]
  53. Régis Leveugle
    Early Analysis of Fault-based Attack Effects in Secure Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2007, v:56, n:10, pp:1431-1434 [Journal]
  54. Régis Leveugle, Glenn H. Chapman
    Special section on defect and fault tolerance in VLSI systems. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2003, v:34, n:1, pp:1- [Journal]
  55. Abdelaziz Ammari, K. Hadjiat, Régis Leveugle
    Combined Fault Classification and Error Propagation Analysis to Refine RT-Level Dependability Evaluation. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:4, pp:365-376 [Journal]

  56. Statistical fault injection: Quantified error and confidence. [Citation Graph (, )][DBLP]


  57. Evaluation of Register-Level Protection Techniques for the Advanced Encryption Standard by Multi-Level Fault Injections. [Citation Graph (, )][DBLP]


  58. Effective Checkpoint and Rollback Using Hardware/OS Collaboration. [Citation Graph (, )][DBLP]


  59. Complementary Formal Approaches for Dependability Analysis. [Citation Graph (, )][DBLP]


  60. A Novel Double-Data-Rate AES Architecture Resistant against Fault Injection. [Citation Graph (, )][DBLP]


  61. Software Self-Testing of a Symmetric Cipher with Error Detection Capability. [Citation Graph (, )][DBLP]


  62. Detailed Analyses of Single Laser Shot Effects in the Configuration of a Virtex-II FPGA. [Citation Graph (, )][DBLP]


  63. Towards automated fault pruning with Petri Nets. [Citation Graph (, )][DBLP]


  64. Robustness evaluation and improvements under laser-based fault attacks of an AES crypto-processor implemented on a SRAM-based FPGA. [Citation Graph (, )][DBLP]


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