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Supamas Sirichotiyakul:
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Publications of Author
- Rafi Levy, David Blaauw, Gabi Braca, Aurobindo Dasgupta, Amir Grinshpon, Chanhee Oh, Boaz Orshav, Supamas Sirichotiyakul, Vladimir Zolotov
ClariNet: a noise analysis tool for deep submicron design. [Citation Graph (0, 0)][DBLP] DAC, 2000, pp:233-238 [Conf]
- Supamas Sirichotiyakul, David Blaauw, Chanhee Oh, Rafi Levy, Vladimir Zolotov, Jingyan Zuo
Driver Modeling and Alignment for Worst-Case Delay Noise. [Citation Graph (0, 0)][DBLP] DAC, 2001, pp:720-725 [Conf]
- Supamas Sirichotiyakul, Tim Edwards, Chanhee Oh, Jingyan Zuo, Abhijit Dharchoudhury, Rajendran Panda, David Blaauw
Stand-by Power Minimization Through Simultaneous Threshold Voltage Selection and Circuit Sizing. [Citation Graph (0, 0)][DBLP] DAC, 1999, pp:436-441 [Conf]
- Sarma B. K. Vrudhula, David Blaauw, Supamas Sirichotiyakul
Estimation of the likelihood of capacitive coupling noise. [Citation Graph (0, 0)][DBLP] DAC, 2002, pp:653-658 [Conf]
- Alexey Glebov, Sergey Gavrilov, David Blaauw, Supamas Sirichotiyakul, Chanhee Oh, Vladimir Zolotov
False-Noise Analysis using Logic Implications. [Citation Graph (0, 0)][DBLP] ICCAD, 2001, pp:515-0 [Conf]
- Vladimir Zolotov, David Blaauw, Supamas Sirichotiyakul, Murat R. Becer, Chanhee Oh, Rajendran Panda, Amir Grinshpon, Rafi Levy
Noise propagation and failure criteria for VLSI designs. [Citation Graph (0, 0)][DBLP] ICCAD, 2002, pp:587-594 [Conf]
- David Blaauw, Abhijit Dharchoudhury, Rajendran Panda, Supamas Sirichotiyakul, Chanhee Oh, Tim Edwards
Emerging power management tools for processor design. [Citation Graph (0, 0)][DBLP] ISLPED, 1998, pp:143-148 [Conf]
- Murat R. Becer, David Blaauw, Supamas Sirichotiyakul, Chanhee Oh, Vladimir Zolotov, Jingyan Zuo, Rafi Levy, Ibrahim N. Hajj
A Global Driver Sizing Tool for Functional Crosstalk Noise Avoidance. [Citation Graph (0, 0)][DBLP] ISQED, 2001, pp:158-0 [Conf]
- Sarma B. K. Vrudhula, David T. Blaauw, Supamas Sirichotiyakul
Probabilistic analysis of interconnect coupling noise. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:9, pp:1188-1203 [Journal]
- Supamas Sirichotiyakul, Tim Edwards, Chanhee Oh, Rajendran Panda, David Blaauw
Duet: an accurate leakage estimation and optimization tool for dual-Vt circuits. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2002, v:10, n:2, pp:79-90 [Journal]
- David Blaauw, Supamas Sirichotiyakul, Chanhee Oh
Driver modeling and alignment for worst-case delay noise. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2003, v:11, n:2, pp:157-166 [Journal]
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