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Tan Yan:
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Publications of Author
- Jing Li, Tan Yan, Bo Yang, Juebang Yu, Chunhui Li
A packing algorithm for non-manhattan hexagon/triangle placement design by using an adaptive o-tree representation. [Citation Graph (0, 0)][DBLP] DAC, 2004, pp:646-651 [Conf]
- Tan Yan, Qing Dong, Yasuhiro Takashima, Yoji Kajitani
How does partitioning matter for 3D floorplanning? [Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2006, pp:73-78 [Conf]
- Tan Yan, Hiroshi Murata
Fast wire length estimation by net bundling for block placement. [Citation Graph (0, 0)][DBLP] ICCAD, 2006, pp:172-178 [Conf]
- Tan Yan, Haruna Murata
A robust and correct computation for the curvilinear routing problem. [Citation Graph (0, 0)][DBLP] ISCAS (6), 2005, pp:5678-5681 [Conf]
- Tan Yan, Shigetoshi Nakatake, Takashi Nojima
Formulating the Empirical Strategies in Module Generation of Analog MOS Layout. [Citation Graph (0, 0)][DBLP] ISVLSI, 2006, pp:44-49 [Conf]
A Theoretical Study on Wire Length Estimation Algorithms for Placement with Opaque Blocks. [Citation Graph (, )][DBLP]
Automatic bus planner for dense PCBs. [Citation Graph (, )][DBLP]
A correct network flow model for escape routing. [Citation Graph (, )][DBLP]
An optimal algorithm for finding disjoint rectangles and its application to PCB routing. [Citation Graph (, )][DBLP]
Optimal bus sequencing for escape routing in dense PCBs. [Citation Graph (, )][DBLP]
Untangling twisted nets for bus routing. [Citation Graph (, )][DBLP]
BSG-Route: a length-matching router for general topology. [Citation Graph (, )][DBLP]
Optimal layer assignment for escape routing of buses. [Citation Graph (, )][DBLP]
B-escape: a simultaneous escape routing algorithm based on boundary routing. [Citation Graph (, )][DBLP]
A negotiated congestion based router for simultaneous escape routing. [Citation Graph (, )][DBLP]
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