The SCEAS System
Navigation Menu

Search the dblp DataBase


W. K. Luk: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. W. K. Luk, Donald T. Tang, C. K. Wong
    Hierarchial global wiring for custom chip design. [Citation Graph (0, 0)][DBLP]
    DAC, 1986, pp:481-489 [Conf]
  2. W. K. Luk, Y. Katayama, Wei Hwang, M. Wordeman, T. Kirihata, Akashi Satoh, Seiji Munetoh, H. Wong, B. El-Kareh, P. Xiao, Rajiv V. Joshi
    Development of a High Bandwidth Merged Logic/DRAM Multimedia Chip. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:279-285 [Conf]
  3. Markku Tamminen, W. K. Luk, Paolo Sipala, Lin S. Woo, C. K. Wong
    Constructing Maximal Slicings from Geometry. [Citation Graph (0, 0)][DBLP]
    Acta Inf., 1986, v:23, n:3, pp:267-288 [Journal]
  4. W. K. Luk, Paolo Sipala, C. K. Wong
    Minimum-Area Wiring for Slicing Structures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1987, v:36, n:6, pp:745-760 [Journal]
  5. W. K. Luk, Paolo Sipala, Markku Tamminen, Donald T. Tang, Lin S. Woo, Chak-Kuen Wong
    A Hierarchical Global Wiring Algorithm for Custom Chip Design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:4, pp:518-533 [Journal]

  6. Synchronization and sensitivity enhancement of the Hodgkin-Huxley neurons due to inhibitory inputs. [Citation Graph (, )][DBLP]

Search in 0.019secs, Finished in 0.020secs
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002