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Jianfeng Luo: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jianfeng Luo, Subarna Sinha, Qing Su, Jamil Kawa, Charles Chiang
    An IC manufacturing yield model considering intra-die variations. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:749-754 [Conf]
  2. Jianfeng Luo, Qing Su, Charles Chiang, Jamil Kawa
    A layout dependent full-chip copper electroplating topography model. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:133-140 [Conf]
  3. Debjit Sinha, Jianfeng Luo, Subramanian Rajagopalan, Shabbir H. Batterywala, Narendra V. Shenoy, Hai Zhou
    Impact of Modern Process Technologies on the Electrical Parameters of Interconnects. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:875-880 [Conf]

  4. Model Based Layout Pattern Dependent Metal Filling Algorithm for Improved Chip Surface Uniformity in the Copper Process. [Citation Graph (, )][DBLP]


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