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Jamil Kawa: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jianfeng Luo, Subarna Sinha, Qing Su, Jamil Kawa, Charles Chiang
    An IC manufacturing yield model considering intra-die variations. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:749-754 [Conf]
  2. Yehia Massoud, Jamil Kawa, Don MacMillen, Jacob White
    Modeling and Analysis of Differential Signaling for Minimizing Inductive Cross-Talk. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:804-809 [Conf]
  3. Narendra V. Shenoy, Jamil Kawa, Raul Camposano
    Design automation for mask programmable fabrics. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:192-197 [Conf]
  4. Dan Page, Jamil Kawa, Charles Chiang
    DFM: swimming upstream. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:1- [Conf]
  5. Jamil Kawa, Charles Chiang
    DFM issues for 65nm and beyond. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:318-322 [Conf]
  6. Jianfeng Luo, Qing Su, Charles Chiang, Jamil Kawa
    A layout dependent full-chip copper electroplating topography model. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:133-140 [Conf]
  7. Bo-Kyung Choi, Charles Chiang, Jamil Kawa, Majid Sarrafzadeh
    Routing resources consumption on M-arch and X-arch. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:73-76 [Conf]
  8. Xin Wang, Charles Chiang, Jamil Kawa, Qing Su
    A Min-Variance Iterative Method for Fast Smart Dummy Feature Density Assignment in Chemical-Mechanical Polishing. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:258-263 [Conf]
  9. Qing Su, Jamil Kawa, Charles Chiang, Yehia Massoud
    Accurate modeling of substrate resistive coupling for floating substrates. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:1, pp:44-51 [Journal]
  10. Yehia Massoud, Steve S. Majors, Jamil Kawa, Tareq Bustami, Don MacMillen, Jacob K. White
    Managing on-chip inductive effects. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:789-798 [Journal]

  11. An innovative Steiner tree based approach for polygon partitioning. [Citation Graph (, )][DBLP]

  12. Automated design of tunable impedance matching networks for reconfigurable wireless applications. [Citation Graph (, )][DBLP]

  13. Who solves the variability problem? [Citation Graph (, )][DBLP]

  14. Impact of dummy filling techniques on interconnect capacitance and planarization in nano-scale process technology. [Citation Graph (, )][DBLP]

  15. Robust reconfigurable filter design using analytic variability quantification techniques. [Citation Graph (, )][DBLP]

  16. Investigating the Impact of Fill Metal on Crosstalk-Induced Delay and Noise. [Citation Graph (, )][DBLP]

  17. Hotspot Based Yield Prediction with Consideration of Correlations. [Citation Graph (, )][DBLP]

  18. Three DFM Challenges: Random Defects, Thickness Variation, and Printability Variation. [Citation Graph (, )][DBLP]

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