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Naresh Maheshwari: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Naresh Maheshwari, Sachin S. Sapatnekar
    An Improved Algorithm for Minimum-Area Retiming. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:2-7 [Conf]
  2. Naresh Maheshwari, Sachin S. Sapatnekar
    Efficient Minarea Retiming of Large Level-Clocked Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:840-0 [Conf]
  3. Naresh Maheshwari, Sachin S. Sapatnekar
    Minimum area retiming with equivalent initial states. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:216-219 [Conf]
  4. Naresh Maheshwari, Sachin S. Sapatnekar
    A Practical Algorithm for Retiming Level-Clocked Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:440-0 [Conf]
  5. Naresh Maheshwari, Sachin S. Sapatnekar
    Retiming control logic. [Citation Graph (0, 0)][DBLP]
    Integration, 1999, v:28, n:1, pp:33-53 [Journal]
  6. Naresh Maheshwari, Sachin S. Sapatnekar
    Optimizing large multiphase level-clocked circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:9, pp:1249-1264 [Journal]

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