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Amitava Majumdar :
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Amitava Majumdar , Wei-Yu Chen , Jun Guo Hold time validation on silicon and the relevance of hazards in timing analysis. [Citation Graph (0, 0)][DBLP ] DAC, 2006, pp:326-331 [Conf ] Amitava Majumdar , Sarma Sastry On the Distribution of Fault Coverage and Test length in Random Testing of Combinational Circuits. [Citation Graph (0, 0)][DBLP ] DAC, 1992, pp:341-346 [Conf ] Sarma Sastry , Amitava Majumdar A Branching Process Model for Observability Analysis of Combinational Circuits. [Citation Graph (0, 0)][DBLP ] DAC, 1991, pp:452-457 [Conf ] Dimitrios Kagaris , Spyros Tragoudas , Amitava Majumdar On-Chip Test Embedding for Multi-Weighted Random LFSRs. [Citation Graph (0, 0)][DBLP ] DFT, 1998, pp:135-0 [Conf ] Amitava Majumdar , Adam Birnbaum , Dong Ju Choi , Abhishek Trivedi , Simon K. Warfield , Kim Baldridge , Petr Krysl A Dynamic Data Driven Grid System for Intra-operative Image Guided Neurosurgery. [Citation Graph (0, 0)][DBLP ] International Conference on Computational Science (2), 2005, pp:672-679 [Conf ] Amitava Majumdar WRAPTure: A Tool for Evaluation and Optimization of Weights for Weighted Random Pattern Testing. [Citation Graph (0, 0)][DBLP ] ICCD, 1994, pp:288-291 [Conf ] Kamran Zarrineh , Thomas A. Ziaja , Amitava Majumdar Automatic Generation and Validation of Memory Test Models for High Performance Microprocessors. [Citation Graph (0, 0)][DBLP ] ICCD, 2001, pp:526-529 [Conf ] Tharaka Devadithya , Kim Baldridge , Adam Birnbaum , Amitava Majumdar , Dong Ju Choi , Richard Wolski , Simon K. Warfield , Neculai Archip On-Demand High Performance Computing: Image Guided Neuro-Surgery Feasibility Study. [Citation Graph (0, 0)][DBLP ] ICPADS (2), 2006, pp:97-102 [Conf ] Amitava Majumdar arallel Performance Study of Monte Carlo Photon Transport Code on Shared-, Distributed-, and Distributed-Shared-Memory Architectures. [Citation Graph (0, 0)][DBLP ] IPDPS, 2000, pp:93-0 [Conf ] Olivier Caty , Ismet Bayraktaroglu , Amitava Majumdar , Richard Lee , John Bell , Lisa Curhan Instruction Based BIST for Board/System Level Test of External Memories and Internconnects. [Citation Graph (0, 0)][DBLP ] ITC, 2003, pp:961-970 [Conf ] Ishwar Parulkar , Thomas A. Ziaja , Rajesh Pendurkar , Anand D'Souza , Amitava Majumdar A Scalable, Low Cost Design-for-Test Architecture for UltraSPARC? Chip Multi-Processors. [Citation Graph (0, 0)][DBLP ] ITC, 2002, pp:726-735 [Conf ] Amitava Majumdar , Sarma Sastry Statistical Analysis of Controllability. [Citation Graph (0, 0)][DBLP ] VLSI Design, 1993, pp:55-60 [Conf ] Amitava Majumdar , Michio Komoda , Tim Ayres Ground Bounce Considerations in DC Parametric Test Generation Using Boundary Scan. [Citation Graph (0, 0)][DBLP ] VTS, 1998, pp:86-91 [Conf ] Amitava Majumdar , Sarma Sastry Probabilistic characterization of controllability in general homogeneous circuits. [Citation Graph (0, 0)][DBLP ] Computer-Aided Design, 1993, v:25, n:2, pp:76-93 [Journal ] Rahul Simha , Amitava Majumdar An urn model with applications to database performance evaluation. [Citation Graph (0, 0)][DBLP ] Computers & OR, 1997, v:24, n:4, pp:289-300 [Journal ] Dimitri Kagaris , Spyros Tragoudas , Amitava Majumdar Test-set partitioning for multi-weighted random LFSRs. [Citation Graph (0, 0)][DBLP ] Integration, 2000, v:30, n:1, pp:65-75 [Journal ] Rahul Simha , Amitava Majumdar On Lookahead in the List Update Problem. [Citation Graph (0, 0)][DBLP ] Inf. Process. Lett., 1994, v:50, n:2, pp:105-110 [Journal ] Dimitrios Kagaris , Spyros Tragoudas , Amitava Majumdar On the Use of Counters for Reproducing Deterministic Test Sets. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1996, v:45, n:12, pp:1405-1419 [Journal ] Amitava Majumdar On Evaluating and Optimizing Weights for Weighted Random Pattern Testing. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1996, v:45, n:8, pp:904-916 [Journal ] Amitava Majumdar , Sarma B. K. Vrudhula Fault Coverage and Test Length Estimation for Random Pattern Testing. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1995, v:44, n:2, pp:234-247 [Journal ] Sarma Sastry , Amitava Majumdar Test efficiency analysis of random self-test of sequential circuits. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:3, pp:390-398 [Journal ] Yuni K. Dewaraja , Michael Ljungberg , Amitava Majumdar , Abhijit Bose , Kenneth F. Koral A parallel Monte Carlo code for planar and SPECT imaging: implementation, verification and applications in 131 I SPECT. [Citation Graph (0, 0)][DBLP ] Computer Methods and Programs in Biomedicine, 2002, v:67, n:2, pp:115-124 [Journal ] Yifeng Cui , Reagan Moore , Kim Olsen , Amit Chourasia , Philip Maechling , Bernard Minster , Steven Day , Yuanfang Hu , Jing Zhu , Amitava Majumdar , Thomas Jordan Enabling Very-Large Scale Earthquake Simulations on Parallel Machines. [Citation Graph (0, 0)][DBLP ] International Conference on Computational Science (1), 2007, pp:46-53 [Conf ] Amitava Majumdar , Sarma B. K. Vrudhula Analysis of signal probability in logic circuits using stochastic models. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 1993, v:1, n:3, pp:365-379 [Journal ] Quantifying performance benefits of overlap using MPI-2 in a seismic modeling application. [Citation Graph (, )][DBLP ] Search in 0.002secs, Finished in 0.304secs