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Xun Liu: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Xun Liu, Marios C. Papaefthymiou
    Design of a high-throughput low-power IS95 Viterbi decoder. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:263-268 [Conf]
  2. Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman
    Maximizing Performance by Retiming and Clock Skew Scheduling. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:231-236 [Conf]
  3. Xun Liu, Yuantao Peng, Marios C. Papaefthymiou
    Practical repeater insertion for low power: what repeater library do we need? [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:30-35 [Conf]
  4. Yuantao Peng, Xun Liu
    Freeze: engineering a fast repeater insertion solver for power minimization using the ellipsoid method. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:813-818 [Conf]
  5. Yuantao Peng, Xun Liu
    Low-power repeater insertion with both delay and slew rate constraints. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:302-307 [Conf]
  6. Xun Liu, Marios C. Papaefthymiou
    A static power estimation methodolodgy for IP-based design. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:280-289 [Conf]
  7. Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman
    Minimizing Sensitivity to Delay Variations in High-Performance Synchronous Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:643-649 [Conf]
  8. Xun Liu, Yuantao Peng, Marios C. Papaefthymiou
    RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1330-1335 [Conf]
  9. Yuantao Peng, Xun Liu
    Power macromodeling of global interconnects considering practical repeater insertion. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:244-247 [Conf]
  10. Yuantao Peng, Xun Liu
    A sensitivity analysis of low-power repeater insertion. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:244-247 [Conf]
  11. Zhentao Yu, Marios C. Papaefthymiou, Xun Liu
    Skew spreading for peak current reduction. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:461-464 [Conf]
  12. Xun Liu, Marios C. Papaefthymiou
    A Markov chain sequence generator for power macromodeling. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:404-411 [Conf]
  13. Lifang Wu, Xianglong Meng, Xun Liu, Shiju Chen
    A New Method of Object Segmentation in the Basketball Videos. [Citation Graph (0, 0)][DBLP]
    ICPR (1), 2006, pp:319-322 [Conf]
  14. Xun Liu, Marios C. Papaefthymiou
    Incorporation of input glitches into power macromodeling. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:846-849 [Conf]
  15. Zhengtao Yu, Xun Liu
    Power Analysis of Rotary Clock. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:150-155 [Conf]
  16. Yuantao Peng, Xun Liu
    RITC: Repeater Insertion with Timing Target Compensation. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:299-300 [Conf]
  17. Xun Liu, Yang Gao, Dong Shao, Ruili Wang
    Feedback based Dynamic Autonomous Web Service Composition. [Citation Graph (0, 0)][DBLP]
    SKG, 2005, pp:19- [Conf]
  18. Xun Liu, Marios C. Papaefthymiou
    A Markov chain sequence generator for power macromodeling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:7, pp:1048-1062 [Journal]
  19. Xun Liu, Marios C. Papaefthymiou
    HyPE: hybrid power estimation for IP-based systems-on-chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:7, pp:1089-1103 [Journal]
  20. Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman
    Retiming and clock scheduling for digital circuit optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:2, pp:184-203 [Journal]
  21. Xun Liu, Yuantao Peng, Marios C. Papaefthymiou
    Practical repeater insertion for low power: what repeater library do we need? [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:5, pp:917-924 [Journal]
  22. Zhengtao Yu, Xun Liu
    Design of Rotary Clock Based Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:43-48 [Conf]
  23. Xun Liu, Yuantao Peng, Marios C. Papaefthymiou
    RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  24. Zhengtao Yu, Xun Liu
    Low-Power Rotary Clock Array Design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:1, pp:5-12 [Journal]
  25. Xun Liu, Marios C. Papaefthymiou
    Design of a 20-mb/s 256-state Viterbi decoder. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:6, pp:965-975 [Journal]

  26. Better than optimum?: register reduction using idle pipelined functional units. [Citation Graph (, )][DBLP]


  27. Compatibility path based binding algorithm for interconnect reduction in high level synthesis. [Citation Graph (, )][DBLP]


  28. Hindrances to the Development of Tourism E-Commerce in China. [Citation Graph (, )][DBLP]


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