The SCEAS System
| |||||||

## Search the dblp DataBase
Michael Orshansky:
[Publications]
[Author Rank by year]
[Co-authors]
[Prefers]
[Cites]
[Cited by]
## Publications of Author- Murari Mani, Anirudh Devgan, Michael Orshansky
**An efficient algorithm for statistical minimization of total power under timing yield constraints.**[Citation Graph (0, 0)][DBLP] DAC, 2005, pp:309-314 [Conf] - Michael Orshansky, Arnab Bandyopadhyay
**Fast statistical timing analysis handling arbitrary delay correlations.**[Citation Graph (0, 0)][DBLP] DAC, 2004, pp:337-342 [Conf] - Michael Orshansky, James C. Chen, Chenming Hu
**A Statistical Performance Simulation Methodology for VLSI Circuits.**[Citation Graph (0, 0)][DBLP] DAC, 1998, pp:402-407 [Conf] - Michael Orshansky, Kurt Keutzer
**A general probabilistic framework for worst case timing analysis.**[Citation Graph (0, 0)][DBLP] DAC, 2002, pp:556-561 [Conf] - Ashish Kumar Singh, Murari Mani, Ruchir Puri, Michael Orshansky
**Gain-based technology mapping for minimum runtime leakage under input vector uncertainty.**[Citation Graph (0, 0)][DBLP] DAC, 2006, pp:522-527 [Conf] - Wei-Shen Wang, Vladik Kreinovich, Michael Orshansky
**Statistical timing based on incomplete probabilistic descriptions of parameter uncertainty.**[Citation Graph (0, 0)][DBLP] DAC, 2006, pp:161-166 [Conf] - Joonsoo Kim, Michael Orshansky
**Towards formal probabilistic power-performance design space exploration.**[Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2006, pp:229-234 [Conf] - Murari Mani, Mahesh Sharma, Michael Orshansky
**Application of fast SOCP based statistical sizing in the microprocessor design flow.**[Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2006, pp:372-375 [Conf] - Rajeshwary Tayade, Vijay Kiran Kalyanam, Sani R. Nassif, Michael Orshansky, Jacob Abraham
**Estimating path delay distribution considering coupling noise.**[Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2007, pp:61-66 [Conf] - Michael Orshansky, Linda Milor, Pinhong Chen, Kurt Keutzer, Chenming Hu
**Impact of Systematic Spatial Intra-Chip Gate Length Variability on Performance of High-Speed Digital Circuits.**[Citation Graph (0, 0)][DBLP] ICCAD, 2000, pp:62-67 [Conf] - Ashish Kumar Singh, Murari Mani, Michael Orshansky
**Statistical technology mapping for parametric yield.**[Citation Graph (0, 0)][DBLP] ICCAD, 2005, pp:511-518 [Conf] - Anand Ramalingam, Gi-Joon Nam, Ashish Kumar Singh, Michael Orshansky, Sani R. Nassif, David Z. Pan
**An accurate sparse matrix based framework for statistical static timing analysis.**[Citation Graph (0, 0)][DBLP] ICCAD, 2006, pp:231-236 [Conf] - Murari Mani, Ashish Kumar Singh, Michael Orshansky
**Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization.**[Citation Graph (0, 0)][DBLP] ICCAD, 2006, pp:19-26 [Conf] - Wei-Shen Wang, Michael Orshansky
**Robust estimation of parametric yield under limited descriptions of uncertainty.**[Citation Graph (0, 0)][DBLP] ICCAD, 2006, pp:884-890 [Conf] - Bin Zhang, Ari Arapostathis, Sani R. Nassif, Michael Orshansky
**Analytical modeling of SRAM dynamic stability.**[Citation Graph (0, 0)][DBLP] ICCAD, 2006, pp:315-322 [Conf] - Murari Mani, Michael Orshansky
**A New Statistical Optimization Algorithm for Gate Sizing.**[Citation Graph (0, 0)][DBLP] ICCD, 2004, pp:272-277 [Conf] - Michael Liu, Wei-Shen Wang, Michael Orshansky
**Leakage power reduction by dual-vth designs under probabilistic analysis of vth variation.**[Citation Graph (0, 0)][DBLP] ISLPED, 2004, pp:2-7 [Conf] - David Nguyen, Abhijit Davare, Michael Orshansky, David G. Chinnery, Brandon Thompson, Kurt Keutzer
**Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization.**[Citation Graph (0, 0)][DBLP] ISLPED, 2003, pp:158-163 [Conf] - Keith A. Bowman, Michael Orshansky, Sachin S. Sapatnekar
**Tutorial II: Variability and Its Impact on Design.**[Citation Graph (0, 0)][DBLP] ISQED, 2006, pp:5- [Conf] - Bin Zhang, Wei-Shen Wang, Michael Orshansky
**FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs.**[Citation Graph (0, 0)][DBLP] ISQED, 2006, pp:755-760 [Conf] - Michael Orshansky, Wei-Shen Wang, Martine Ceberio, Gang Xiang
**Interval-based robust statistical techniques for non-negative convex functions, with application to timing analysis of computer chips.**[Citation Graph (0, 0)][DBLP] SAC, 2006, pp:1645-1649 [Conf] - Kurt Keutzer, Michael Orshansky
**From blind certainty to informed uncertainty.**[Citation Graph (0, 0)][DBLP] Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:37-41 [Conf] - Michael Orshansky, Linda Milor, Pinhong Chen, Kurt Keutzer, Chenming Hu
**Impact of spatial intrachip gate length variability on theperformance of high-speed digital circuits.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:5, pp:544-553 [Journal] - Anand Ramalingam, Ashish Kumar Singh, Sani R. Nassif, Michael Orshansky, David Z. Pan
**Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing Analysis.**[Citation Graph (0, 0)][DBLP] DAC, 2007, pp:148-153 [Conf] - Ashish Kumar Singh, Adnan Aziz, Sriram Vishwanath, Michael Orshansky
**Generation of Efficient Codes for Realizing Boolean Functions in Nanotechnologies**[Citation Graph (0, 0)][DBLP] CoRR, 2007, v:0, n:, pp:- [Journal] - Kypros Constantinides, Stephen Plaza, Jason A. Blome, Valeria Bertacco, Scott A. Mahlke, Todd M. Austin, Bin Zhang, Michael Orshansky
**Architecting a reliable CMP switch architecture.**[Citation Graph (0, 0)][DBLP] TACO, 2007, v:4, n:1, pp:- [Journal] - Wei-Shen Wang, Michael Liu, Michael Orshansky
**Analysis of Leakage Power Reduction in Dual-Vth Technologies in the Presence of Large Threshold Voltage Variation.**[Citation Graph (0, 0)][DBLP] J. Low Power Electronics, 2006, v:2, n:1, pp:1-7 [Journal] - Wei-Shen Wang, Michael Orshansky
**Estimation of Leakage Power Consumption and Parametric Yield Based on Realistic Probabilistic Descriptions of Parameters.**[Citation Graph (0, 0)][DBLP] J. Low Power Electronics, 2007, v:3, n:1, pp:1-12 [Journal] **A methodology for propagating design tolerances to shape tolerances for use in manufacturing.**[Citation Graph (, )][DBLP]**BulletProof: a defect-tolerant CMP switch architecture.**[Citation Graph (, )][DBLP]**Electrically driven optical proximity correction based on linear programming.**[Citation Graph (, )][DBLP]**Mitigation of intra-array SRAM variability using adaptive voltage architecture.**[Citation Graph (, )][DBLP]**NBTI-aware DVFS: a new approach to saving energy and increasing processor lifetime.**[Citation Graph (, )][DBLP]**Modeling of NBTI-Induced PMOS Degradation under Arbitrary Dynamic Temperature Variation.**[Citation Graph (, )][DBLP]**Statistical analysis of circuit timing using majorization.**[Citation Graph (, )][DBLP]**The Search for Alternative Computational Paradigms.**[Citation Graph (, )][DBLP]
Search in 0.039secs, Finished in 0.040secs | |||||||

| |||||||

| |||||||

System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002 for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002 |