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Weiwei Mao: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Weiwei Mao, Michael D. Ciletti
    Dytest: A Self-Learning Algorithm Using Dynamic Testability Measures to Accelerate Test Generation. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:591-596 [Conf]
  2. Weiwei Mao, Michael D. Ciletti
    A Simplified Six-waveform Type Method for Delay Fault Testing. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:730-733 [Conf]
  3. Weiwei Mao, Michael D. Ciletti
    A Variable Observation Time Method for Testing Delay Faults. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:728-731 [Conf]
  4. Weiwei Mao, Michael D. Ciletti
    Correlation-Reduced Scan-path Design To Improve Delay Fault Coverage. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:73-79 [Conf]
  5. Weiwei Mao, Xieting Ling
    Robust test generation algorithm for stuck-open fault in CMOS circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1986, pp:236-242 [Conf]
  6. Weiwei Mao, Ravi K. Gulati, Deepak K. Goel, Michael D. Ciletti
    QUIETEST: A Quiescent Current Testing Methodology for Detecting Leakage Faults. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:280-283 [Conf]
  7. Ravi K. Gulati, Weiwei Mao, Deepak K. Goel
    Detection of "Undetectable" Faults Using IDDQ Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:770-777 [Conf]
  8. Yunsheng Lu, Weiwei Mao, Ramaswami Dandapani, Ravi K. Gulati
    Structure and Metrology for a Single-wire Analog. [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:919-928 [Conf]
  9. Weiwei Mao, Michael D. Ciletti
    Robustness Enhancement and Detection Threshold Reduction in ATPG for Gate Delay Faults. [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:588-597 [Conf]
  10. Weiwei Mao, Ravi K. Gulati
    Improving Gate Level Fault Coverage by RTL Fault Grading. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:150-159 [Conf]
  11. Weiwei Mao, Michael D. Ciletti
    DYTEST: a self-learning algorithm using dynamic testability measures to accelerate test generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:8, pp:893-898 [Journal]
  12. Weiwei Mao, Michael D. Ciletti
    Reducing correlation to improve coverage of delay faults in scan-path design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:5, pp:638-646 [Journal]

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