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Tareq Bustami: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yehia Massoud, Steve S. Majors, Tareq Bustami, Jacob White
    Layout Techniques for Minimizing On-Chip Interconnect Self Inductance. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:566-571 [Conf]
  2. Yehia Massoud, Steve S. Majors, Jamil Kawa, Tareq Bustami, Don MacMillen, Jacob K. White
    Managing on-chip inductive effects. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:789-798 [Journal]

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