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D. Michael Miller: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. D. Michael Miller, Dmitri Maslov, Gerhard W. Dueck
    A transformation based algorithm for reversible logic synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:318-323 [Conf]
  2. Elena Dubrova, Peeter Ellervee, D. Michael Miller, Jon C. Muzio
    TOP: An Algorithm for Three-Level Optimization of PLDs. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:751- [Conf]
  3. Dmitri Maslov, Christina Young, D. Michael Miller, Gerhard W. Dueck
    Quantum Circuit Simplification Using Templates. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1208-1213 [Conf]
  4. Whitney J. Townsend, Mitchell A. Thornton, Rolf Drechsler, D. Michael Miller
    Computing walsh, arithmetic, and reed-muller spectral decision diagrams using graph transformations. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2002, pp:178-183 [Conf]
  5. Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller
    Fredkin/Toffoli Templates for Reversible Logic Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:256-261 [Conf]
  6. Shujian Zhang, R. Byrne, D. Michael Miller
    BIST Generators for Sequential Faults. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:260-263 [Conf]
  7. Shujian Zhang, R. Byrne, Jon C. Muzio, D. Michael Miller
    Why Cellular Automata are better than LFSRs as Built-in Self-test Generators for Sequential-type Faults. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:69-72 [Conf]
  8. Gerhard W. Dueck, D. Michael Miller
    RCM-MVL: A Recursive Consensus MVL Minimization Algorithm. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1990, pp:136-143 [Conf]
  9. D. Michael Miller
    Multiple-Valued Logic Design Tools. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:2-11 [Conf]
  10. D. Michael Miller
    Spectral Transformation of Multiple-Valued Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1994, pp:89-96 [Conf]
  11. D. Michael Miller, Rolf Drechsler
    On the Construction of Multiple-Valued Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:245-253 [Conf]
  12. D. Michael Miller, Gerhard W. Dueck
    On the Size of Multiple-Valued Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2003, pp:235-240 [Conf]
  13. D. Michael Miller, Rolf Drechsler
    Augmented Sifting of Multiple-Valued Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2003, pp:375-382 [Conf]
  14. D. Michael Miller, Gerhard W. Dueck, Dmitri Maslov
    A Synthesis Method for MVL Reversible Logi. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2004, pp:74-80 [Conf]
  15. D. Michael Miller, Noriaki Muranaka
    Multiple-Valued Decision Diagrams with Symmetric Variable Nodes. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1996, pp:242-247 [Conf]
  16. D. Michael Miller, Mitchell A. Thornton
    QMDD: A Decision Diagram Structure for Reversible and Quantum Circuits. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:30- [Conf]
  17. Noriaki Muranaka, Shigenobu Arai, Shigeru Imanishi, D. Michael Miller
    A Ternary Systolic Product-Sum Circuit for GF(3m) using Neuron MOSFETs. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1996, pp:92-97 [Conf]
  18. Noriaki Muranaka, Shigeru Imanishi, D. Michael Miller
    Decimal Addition and Subtraction Units Using the p-Valued Decimal Signed-Digit Number Representation. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:228-233 [Conf]
  19. Yasunori Nagata, D. Michael Miller, Masao Mukaidono
    Logic Synthesis of Controllers for B-Ternary Asynchronous Systems. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2000, pp:402-0 [Conf]
  20. Yasunori Nagata, D. Michael Miller, Masao Mukaidono
    Minimal Test Set Generation for Fault Diagnosis in R-Valued PLAs. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1998, pp:38-0 [Conf]
  21. Yasunori Nagata, D. Michael Miller, Masao Mukaidono
    B-ternary Logic Based Asynchronous Micropipeline. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1999, pp:214-219 [Conf]
  22. Mitchell A. Thornton, D. Michael Miller, Whitney J. Townsend
    Chrestenson Spectrum Computation Using Cayley Color Graphs. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:123-129 [Conf]
  23. R. Tomczuk, D. Michael Miller
    Autocorrelation Techniques for Multi-Bit Decoder PLAs. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1992, pp:355-364 [Conf]
  24. Mitchell A. Thornton, Rolf Drechsler, D. Michael Miller
    Multi-Output Timed Shannon Circuits. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2002, pp:47-52 [Conf]
  25. Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller
    Simplification of Toffoli Networks via Templates. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:53-0 [Conf]
  26. D. Michael Miller, Jon C. Muzio
    Spectral Fault Signatures for Internally Unate Combinational Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1983, v:32, n:11, pp:1058-1062 [Journal]
  27. D. Michael Miller, Jon C. Muzio
    Spectral Fault Signatures for Single Stuck-At Faults in Combinational Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1984, v:33, n:8, pp:765-769 [Journal]
  28. Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller
    Toffoli network synthesis with templates. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:6, pp:807-817 [Journal]
  29. D. Michael Miller
    An improved method for computing a generalized spectral coefficient. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:3, pp:233-238 [Journal]
  30. Micaela Serra, Terry Slater, Jon C. Muzio, D. Michael Miller
    The analysis of one-dimensional linear cellular automata and their aliasing properties. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:7, pp:767-778 [Journal]
  31. Shujian Zhang, D. Michael Miller, Jon C. Muzio
    Notes on "Complexity of the lookup-table minimization problem for FPGA technology mapping". [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:12, pp:1588-1590 [Journal]
  32. Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller
    Synthesis of Fredkin-Toffoli reversible networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:6, pp:765-769 [Journal]
  33. Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller
    Techniques for the synthesis of reversible Toffoli networks. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:4, pp:- [Journal]

  34. Partially Redundant Logic Detection Using Symbolic Equivalence Checking in Reversible and Irreversible Logic Circuits. [Citation Graph (, )][DBLP]


  35. Synthesizing Reversible Circuits for Irreversible Functions. [Citation Graph (, )][DBLP]


  36. A Heterogeneous Decision Diagram Package. [Citation Graph (, )][DBLP]


  37. Variable Reordering and Sifting for QMDD. [Citation Graph (, )][DBLP]


  38. Quantum Logic Implementation of Unary Arithmetic Operations. [Citation Graph (, )][DBLP]


  39. On the Data Structure Metrics of Quantum Multiple-Valued Decision Diagrams. [Citation Graph (, )][DBLP]


  40. Equivalence Checking of Reversible Circuits. [Citation Graph (, )][DBLP]


  41. Reducing Reversible Circuit Cost by Adding Lines. [Citation Graph (, )][DBLP]


  42. Heterogeneous Decision Diagrams for Applications in Harmonic Analysis on Finite Non-Abelian Groups. [Citation Graph (, )][DBLP]


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