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Gerhard W. Dueck: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. D. Michael Miller, Dmitri Maslov, Gerhard W. Dueck
    A transformation based algorithm for reversible logic synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:318-323 [Conf]
  2. Dmitri Maslov, Christina Young, D. Michael Miller, Gerhard W. Dueck
    Quantum Circuit Simplification Using Templates. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1208-1213 [Conf]
  3. Daniel Große, Xiaobo Chen, Gerhard W. Dueck, Rolf Drechsler
    Exact sat-based toffoli network synthesis. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:96-101 [Conf]
  4. Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller
    Fredkin/Toffoli Templates for Reversible Logic Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:256-261 [Conf]
  5. Gerhard W. Dueck
    Direct Cover MVL Minimization with Cost-Tables. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1992, pp:58-65 [Conf]
  6. Gerhard W. Dueck, Jon T. Butler
    Multiple-Valued Logic Operations with Universal Literals. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1994, pp:73-79 [Conf]
  7. Gerhard W. Dueck, Robert C. Earle, Parthasarathy P. Tirumalai, Jon T. Butler
    Multiple-Valued Programmable Logic Array Minmization by Simulated Annealing. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1992, pp:66-74 [Conf]
  8. Gerhard W. Dueck, Mou Hu, Blair Fraser
    A Super Switch Algebra for Quantum Device Based Systems. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1999, pp:118-124 [Conf]
  9. Gerhard W. Dueck, D. Michael Miller
    RCM-MVL: A Recursive Consensus MVL Minimization Algorithm. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1990, pp:136-143 [Conf]
  10. Gerhard W. Dueck, G. H. John van Rees
    On the Maximum Number of Implicants Needed to Cover a Multiple-Valued Logic Function Using Window Literals. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1991, pp:280-286 [Conf]
  11. Blair Fraser, Gerhard W. Dueck
    Multiple-Valued Logic Minimization using Universal Literals and Cost Tables. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1998, pp:239-244 [Conf]
  12. D. Michael Miller, Gerhard W. Dueck
    On the Size of Multiple-Valued Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2003, pp:235-240 [Conf]
  13. D. Michael Miller, Gerhard W. Dueck, Dmitri Maslov
    A Synthesis Method for MVL Reversible Logi. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2004, pp:74-80 [Conf]
  14. Svetlana N. Yanushkevich, Jon T. Butler, Gerhard W. Dueck, Vlad P. Shmerko
    Experiments on FPRM Expressions for Partially Symmetric Logic Functions. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2000, pp:141-146 [Conf]
  15. Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller
    Simplification of Toffoli Networks via Templates. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:53-0 [Conf]
  16. Jon T. Butler, Gerhard W. Dueck, Svetlana N. Yanushkevich, Vlad P. Shmerko
    On the number of generators for transeunt triangles. [Citation Graph (0, 0)][DBLP]
    Discrete Applied Mathematics, 2001, v:108, n:3, pp:309-316 [Journal]
  17. Ping Wang, Gerhard W. Dueck, S. MacMillan
    Using simulated annealing to construct extremal graphs. [Citation Graph (0, 0)][DBLP]
    Discrete Mathematics, 2001, v:235, n:1-3, pp:125-135 [Journal]
  18. Jon T. Butler, Gerhard W. Dueck, Vlad P. Shmerko, Svetlana N. Yanushkevich
    Comments on "Sympathy: fast exact minimization of fixedpolarity Reed-Muller expansion for symmetric functions". [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:11, pp:1386-1388 [Journal]
  19. Dmitri Maslov, Gerhard W. Dueck
    Reversible cascades with minimal garbage. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:11, pp:1497-1509 [Journal]
  20. Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller
    Toffoli network synthesis with templates. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:6, pp:807-817 [Journal]
  21. Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller
    Synthesis of Fredkin-Toffoli reversible networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:6, pp:765-769 [Journal]
  22. Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller
    Techniques for the synthesis of reversible Toffoli networks. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:4, pp:- [Journal]

  23. Quantified Synthesis of Reversible Logic. [Citation Graph (, )][DBLP]


  24. Debugging of Toffoli networks. [Citation Graph (, )][DBLP]


  25. Synthesizing Reversible Circuits for Irreversible Functions. [Citation Graph (, )][DBLP]


  26. Pairwise decomposition of toffoli gates in a quantum circuit. [Citation Graph (, )][DBLP]


  27. Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don't Cares. [Citation Graph (, )][DBLP]


  28. RevLib: An Online Resource for Reversible Functions and Reversible Circuits. [Citation Graph (, )][DBLP]


  29. ESOP-Based Toffoli Network Generation with Transformations. [Citation Graph (, )][DBLP]


  30. Toffoli Gate Implementation Using the Billiard Ball Model. [Citation Graph (, )][DBLP]


  31. Reversible Logic Synthesis with Output Permutation. [Citation Graph (, )][DBLP]


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