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Satrajit Chatterjee: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton
    DAG-aware AIG rewriting a fresh look at combinational logic synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:532-535 [Conf]
  2. Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton
    Improvements to technology mapping for LUT-based FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2006, pp:41-49 [Conf]
  3. Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton, Xinning Wang, Timothy Kam
    Reducing structural bias in technology mapping. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:519-526 [Conf]
  4. Satrajit Chatterjee, Robert K. Brayton
    A new incremental placement algorithm and its application to congestion-aware divisor extraction. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:541-548 [Conf]
  5. Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton, Niklas Eén
    Improvements to combinational equivalence checking. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:836-843 [Conf]
  6. Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton
    Factor cuts. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:143-150 [Conf]
  7. Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton, Andreas Kuehlmann
    On Resolution Proofs for Combinational Equivalence. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:600-605 [Conf]

  8. Automatic Generation of Inductive Invariants from High-Level Microarchitectural Models of Communication Fabrics. [Citation Graph (, )][DBLP]


  9. Combinational and sequential mapping with priority cuts. [Citation Graph (, )][DBLP]


  10. Boolean factoring and decomposition of logic networks. [Citation Graph (, )][DBLP]


  11. Physical-Aware Link Allocation and Route Assignment for Chip Multiprocessing. [Citation Graph (, )][DBLP]


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