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Krishna P. Belkhale: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]
Publications of Author
- Krishna P. Belkhale, Prithviraj Banerjee
An Approximate Algorithm for the Partitionable Independent Task Scheduling Problem. [Citation Graph (2, 0)][DBLP]
ICPP (1), 1990, pp:72-75 [Conf] - Cho W. Moon, Harish Kriplani, Krishna P. Belkhale
Timing model extraction of hierarchical blocks by graph reduction. [Citation Graph (0, 0)][DBLP]
DAC, 2002, pp:152-157 [Conf] - Sumit Roy, Krishna P. Belkhale, Prithviraj Banerjee
An Approxmimate Algorithm for Delay-Constraint Technology Mapping. [Citation Graph (0, 0)][DBLP]
DAC, 1999, pp:367-372 [Conf] - Krishna P. Belkhale, Prithviraj Banerjee
A Parallel Algorithm for Hierarchical Circuit Extraction. [Citation Graph (0, 0)][DBLP]
ICCAD, 1990, pp:236-239 [Conf] - Krishna P. Belkhale, Alexander J. Suess
Timing analysis with known false sub graphs. [Citation Graph (0, 0)][DBLP]
ICCAD, 1995, pp:736-740 [Conf] - Krishna P. Belkhale, Prithviraj Banerjee
Geometric Connected Component Labeling on Distributed Memory Multicomputers. [Citation Graph (0, 0)][DBLP]
ICPP (3), 1990, pp:291-294 [Conf] - Krishna P. Belkhale, Prithviraj Banerjee
A Scheduling Algorithm for Parallelizable Dependent Tasks. [Citation Graph (0, 0)][DBLP]
IPPS, 1991, pp:500-506 [Conf] - Krishna P. Belkhale, Prithviraj Banerjee
Reconfiguration Strategies for VLSI Processor Arrays and Trees Using a Modified Diogenes Approach. [Citation Graph (0, 0)][DBLP]
IEEE Trans. Computers, 1992, v:41, n:1, pp:83-96 [Journal] - Krishna P. Belkhale, Prithviraj Banerjee
Parallel Algorithms for Geometric Connected Component Labeling on a Hypercube Multiprocessor. [Citation Graph (0, 0)][DBLP]
IEEE Trans. Computers, 1992, v:41, n:6, pp:699-709 [Journal] - Krishna P. Belkhale, Prithviraj Banerjee
Parallel algorithms for VLSI circuit extraction. [Citation Graph (0, 0)][DBLP]
IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:5, pp:604-618 [Journal] - Krishna P. Belkhale, Randall J. Brouwer, Prithviraj Banerjee
Task scheduling for exploiting parallelism and hierarchy in VLSI CAD algorithms. [Citation Graph (0, 0)][DBLP]
IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:5, pp:557-567 [Journal]
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