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Rajesh Raina: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. James Monaco, David Holloway, Rajesh Raina
    Functional Verification Methodology for the PowerPC 604 Microprocessor. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:319-324 [Conf]
  2. Rajesh Raina, Robert Bailey, Charles Njinda, Robert F. Molyneaux, Charlie Beh
    Efficient Testing of Clock Regenerator Circuits in Scan Designs. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:95-100 [Conf]
  3. Rajesh Raina, Robert F. Molyneaux
    Random Self-Test Method - Applications on PowerPC (tm) Microprocessor Caches. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1998, pp:222-229 [Conf]
  4. Magdy S. Abadir, Rajesh Raina
    Design-for-test methodology for Motorola PowerPC microprocessors. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:810-819 [Conf]
  5. B. Bailey, A. Metayer, B. Svrcek, Nandu Tendolkar, E. Wolf, Eric Fiene, Mike Alexander, Rick Woltenberg, Rajesh Raina
    Test Methodology for Motorola's High Performance e500 Core Based on PowerPC Instruction Set Architecture. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:574-583 [Conf]
  6. Dawit Belete, Ashutosh Razdan, William Schwarz, Rajesh Raina, Christopher Hawkins, Jeff Morehead
    Use of DFT Techniques In Speed Grading a 1GHz+ Microprocessor . [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1111-1119 [Conf]
  7. John Gatej, Lee Song, Carol Pyron, Rajesh Raina, Tom Munns
    valuating ATE Features in Terms of Test Escape Rates and Other Cost of Test Culprits. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1040-1049 [Conf]
  8. Carol Pyron, Mike Alexander, James Golab, George Joos, Bruce Long, Robert F. Molyneaux, Rajesh Raina, Nandu Tendolkar
    DFT advances in the Motorola's MPC7400, a PowerPC G4 microprocessor. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:137-146 [Conf]
  9. Rajesh Raina, Robert Bailey, Dawit Belete, Vikram Khosa, Robert F. Molyneaux, Javier Prado, Ashutosh Razdan
    DFT advances in Motorola's Next-Generation 74xx PowerPCTM microprocessor. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:131-140 [Conf]
  10. Rajesh Raina, Charles Njinda, Robert F. Molyneaux
    How Seriously Do You Take Your Possible-Detect Faults? [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:819-828 [Conf]
  11. Mani Soma, Welela Haileselassie, Jessica Yan, Rajesh Raina
    A Wavelet-Based Timing Parameter Extraction Method. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:120-128 [Conf]
  12. Takahiro J. Yamaguchi, Mani Soma, David Halter, Jim Nissen, Rajesh Raina, Masahiro Ishida, Toshifumi Watanabe
    Jitter measurements of a PowerPCTM microprocessor using an analytic signal method. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:955-964 [Conf]
  13. Takahiro J. Yamaguchi, Mani Soma, Jim Nissen, David Halter, Rajesh Raina, Masahiro Ishida
    Testing clock distribution circuits using an analytic signal method. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:323-331 [Conf]
  14. Nandu Tendolkar, Robert F. Molyneaux, Carol Pyron, Rajesh Raina
    At-Speed Testing of Delay Faults for Motorola's MPC7400, a PowerPC(tm) Microprocessor. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:3-8 [Conf]
  15. Nandu Tendolkar, Rajesh Raina, Rick Woltenberg, Xijiang Lin, Bruce Swanson, Greg Aldrich
    Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC(tm) Instruction Set Architecture. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:3-8 [Conf]
  16. Takahiro J. Yamaguchi, Masahiro Ishida, Mani Soma, David Halter, Rajesh Raina, Jim Nissen
    A Method for Measuring the Cycle-to-Cycle Period Jitter of High-Frequency Clock Signals. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:102-110 [Conf]
  17. Jay Bedsole, Rajesh Raina, Al Crouch, Magdy S. Abadir
    Very Low Cost Testers: Opportunities and Challenges. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2001, v:18, n:5, pp:60-69 [Journal]
  18. Takahiro J. Yamaguchi, Mani Soma, Jim Nissen, David Halter, Rajesh Raina, Masahiro Ishida
    Skew measurements in clock distribution circuits using an analytic signal method. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:7, pp:997-1009 [Journal]

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