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Vasant B. Rao: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Vasant B. Rao
    Delay Analysis of the Distributed RC Line. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:370-375 [Conf]
  2. Youssef Saab, Vasant B. Rao
    An Evolution-Based Approach to Partitioning ASIC Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:767-770 [Conf]
  3. Youssef Saab, Vasant B. Rao
    Stochastic Evolution: a Fast Effective Heuristic for Some Generic Layout Problems. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:26-31 [Conf]
  4. Shun-Lin Su, Vasant B. Rao, Timothy N. Trick
    HPEX: A Hierarchical Parasitic Circuit Extractor. [Citation Graph (0, 0)][DBLP]
    DAC, 1987, pp:566-569 [Conf]
  5. Youssef Saab, Vasant B. Rao
    A Stochastic Algorithm for Circuit Bi-Partitioning. [Citation Graph (0, 0)][DBLP]
    Great Lakes Computer Science Conference, 1989, pp:313-321 [Conf]
  6. Sachin S. Sapatnekar, Vasant B. Rao, Pravin M. Vaidya
    A Convex Optimization Approach to Transistor Sizing for CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:482-485 [Conf]
  7. M. A. Manzoul, Vasant B. Rao
    Multi-Input Fuzzy Inference Engine on a Systolic Array. [Citation Graph (0, 0)][DBLP]
    IEA/AIE (Vol. 2), 1988, pp:958-964 [Conf]
  8. Vasant B. Rao, Jeffrey Soreff, Ravichander Ledalla, Fred L. Yang
    Aggressive crunching of extracted RC netlists. [Citation Graph (0, 0)][DBLP]
    Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:70-77 [Conf]
  9. Yun-Cheng Ju, Vasant B. Rao, Resve A. Saleh
    Consistency checking and optimization of macromodels. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:8, pp:957-967 [Journal]
  10. Vasant B. Rao, Timothy N. Trick
    Network Partitioning and Ordering for MOS VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:1, pp:128-144 [Journal]
  11. Sachin S. Sapatnekar, Vasant B. Rao, Pravin M. Vaidya, Sung-Mo Kang
    An exact solution to the transistor sizing problem for CMOS circuits using convex optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:11, pp:1621-1634 [Journal]
  12. Youssef Saab, Vasant B. Rao
    Fast effective heuristics for the graph bisectioning problem. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:1, pp:91-98 [Journal]
  13. Youssef Saab, Vasant B. Rao
    Combinatorial optimization by stochastic evolution. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:4, pp:525-535 [Journal]

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