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Thomas M. Niermann: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Thomas M. Niermann, Wu-Tung Cheng, Janak H. Patel
    Proofs: A Fast, Memory Efficient Sequential Circuit Fault Simulator. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:535-540 [Conf]
  2. Elizabeth M. Rudnick, Janak H. Patel, Gary S. Greenstein, Thomas M. Niermann
    Sequential Circuit Test Generation in a Genetic Algorithm Framework. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:698-704 [Conf]
  3. Elizabeth M. Rudnick, Thomas M. Niermann, Janak H. Patel
    Methods for Reducing Events in Sequential Circuit Fault Simulation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:546-549 [Conf]
  4. Thomas M. Niermann, Wu-Tung Cheng, Janak H. Patel
    PROOFS: a fast, memory-efficient sequential circuit fault simulator. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:2, pp:198-207 [Journal]
  5. Thomas M. Niermann, Rabindra K. Roy, Janak H. Patel, Jacob A. Abraham
    Test compaction for sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:2, pp:260-267 [Journal]
  6. Elizabeth M. Rudnick, Janak H. Patel, Gary S. Greenstein, Thomas M. Niermann
    A genetic algorithm framework for test generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:9, pp:1034-1044 [Journal]

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