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Sudip Nag: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Sudip Nag, Kaushik Roy
    Iterative Wirability and Performance Improvement for FPGAs. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:321-325 [Conf]
  2. Sudip Nag, Rob A. Rutenbar
    Performance-Driven Simultaneous Place and Route for Row-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:301-307 [Conf]
  3. Sudip Nag, Kamal Chaudhary
    Post-Placement Residual-Overlap Removal with Minimal Movement. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:581-586 [Conf]
  4. Jason Helge Anderson, Sudip Nag, Kamal Chaudhary, Sandor Kalman, Chari Madabhushi, Paul Cheng
    Run-Time-Conscious Automatic Timing-Driven FPGA Layout Synthesis. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:168-178 [Conf]
  5. Jason Helge Anderson, Jim Saunders, Sudip Nag, Chari Madabhushi, Rajeev Jayaraman
    A Placement Algorithm for FPGA Designs with Multiple I/O Standards. [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:211-220 [Conf]
  6. Kaushik Roy, Sudip Nag
    On Channel Architecture and Routability for FPGAs Under Faulty Conditions. [Citation Graph (0, 0)][DBLP]
    FPL, 1994, pp:361-372 [Conf]
  7. Sujoy Mitra, Sudip Nag, Rob A. Rutenbar, L. Richard Carley
    System-level routing of mixed-signal ASICs in WREN. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:394-399 [Conf]
  8. Kaushik Roy, Sudip Nag, Santanu Dutta
    Channel Architecture Optimization for Performance and Routability of Row-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:220-223 [Conf]
  9. Santanu Dutta, Sudip Nag, Kaushik Roy
    ASAP: A Transistor Sizing Tool for Speed Area and Power Optimization of Static CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:61-64 [Conf]
  10. Sudip Nag, H. K. Verma, Kaushik Roy
    VLSI Signal Processing in FPGAs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:609- [Conf]
  11. Kaushik Roy, Sudip Nag
    On Routability for FPGAs under Faulty Conditions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:11, pp:1296-1305 [Journal]
  12. Sudip Nag, Rob A. Rutenbar
    Performance-driven simultaneous placement and routing for FPGA's. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:6, pp:499-518 [Journal]
  13. Kaushik Roy, Sudip Nag
    Automatic synthesis of FPGA channel architecture for routability and performance. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:4, pp:508-511 [Journal]

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