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Naveena Nagi: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Naveena Nagi, Abhijit Chatterjee, Jacob A. Abraham
    DRAFTS: Discretized Analog Circuit Fault Simulator. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:509-514 [Conf]
  2. Naveena Nagi, Abhijit Chatterjee, Ashok Balivada, Jacob A. Abraham
    Fault-based automatic test generator for linear analog circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:88-91 [Conf]
  3. Naveena Nagi, Abhijit Chatterjee, Jacob A. Abraham
    MIXER: Mixed-Signal Fault Simulator. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:568-571 [Conf]
  4. Naveena Nagi, Abhijit Chatterjee, Jacob A. Abraham
    A Signature Analyzer for Analog and Mixed-signal Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:284-287 [Conf]
  5. Stephen K. Sunter, Naveena Nagi
    A Simplified Polynomial-Fitting Algorithm for DAC and ADC BIST. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:389-395 [Conf]
  6. Abhijit Chatterjee, Bruce C. Kim, Naveena Nagi
    Low-cost DC built-in self-test of linear analog circuits using checksums. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:230-233 [Conf]
  7. Abhijit Chatterjee, Naveena Nagi
    Design for Testability and Built-In Self-Test of Mixed-Signal Circuits: A Tutorial. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:388-392 [Conf]
  8. Naveena Nagi, Abhijit Chatterjee, Ashok Balivada, Jacob A. Abraham
    Efficient multisine testing of analog circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:234-238 [Conf]
  9. Stephen K. Sunter, Naveena Nagi
    Test Metrics for Analog Parametric Faults. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:226-235 [Conf]
  10. Pramodchandran N. Variyam, Abhijit Chatterjee, Naveena Nagi
    Low-cost and efficient digital-compatible BIST for analog circuits using pulse response sampling. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:261-266 [Conf]
  11. Heebyung Yoon, Pramodchandran N. Variyam, Abhijit Chatterjee, Naveena Nagi
    Hierarchical Statistical Inference Model for Specification Based Testing of Analog Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:145-151 [Conf]
  12. Abhijit Chatterjee, Bruce C. Kim, Naveena Nagi
    DC Built-In Self-Test for Linear Analog Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:2, pp:26-33 [Journal]
  13. Naveena Nagi, Abhijit Chatterjee, Heebyung Yoon, Jacob A. Abraham
    Signature analysis for analog and mixed-signal circuit test response compaction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:6, pp:540-546 [Journal]

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