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Publications of Author

1. Pierluigi Nuzzo, Geert Van der Plas, Fernando De Bernardinis, Liesbet Van der Perre, Bert Gyselinckx, Pierangelo Terreni
   A 10.6mW/0.8pJ power-scalable 1GS/s 4b ADC in 0.18mum CMOS with 5.8GHz ERBW. [Citation Graph (0, 0)][DBLP]
   DAC, 2006, pp:873-878 [Conf]
   
2. Geert Van der Plas, Mustafa Badaroglu, Gerd Vandersteen, Petr Dobrovolný, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
   High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects. [Citation Graph (0, 0)][DBLP]
   DAC, 2004, pp:854-859 [Conf]
   
3. Geert Van der Plas, Jan Vandenbussche, Walter Daems, Antal van den Bosch, Georges G. E. Gielen, Willy M. C. Sansen
   Systematic design of a 14-bit 150-MS/s CMOS current-steering D/A converter. [Citation Graph (0, 0)][DBLP]
   DAC, 2000, pp:452-457 [Conf]
   
4. Carl De Ranter, B. De Muer, Geert Van der Plas, Peter J. Vancorenland, Michiel Steyaert, Georges G. E. Gielen, Willy M. C. Sansen
   CYCLONE: automated design and layout of RF LC-oscillators. [Citation Graph (0, 0)][DBLP]
   DAC, 2000, pp:11-14 [Conf]
   
5. Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
   Digital Ground Bounce Reduction by Phase Modulation of the Clock. [Citation Graph (0, 0)][DBLP]
   DATE, 2004, pp:88-93 [Conf]
   
6. Charlotte Soens, Geert Van der Plas, Piet Wambacq, Stéphane Donnay
   Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance. [Citation Graph (0, 0)][DBLP]
   DATE, 2005, pp:270-275 [Conf]
   
7. Peter J. Vancorenland, Geert Van der Plas, Michiel Steyaert, Georges G. E. Gielen, Willy M. C. Sansen
   A Layout-Aware Synthesis Methodology for RF Circuits. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2001, pp:358-0 [Conf]
   
8. Wim Verhaegen, Geert Van der Plas, Georges G. E. Gielen
   Automated test pattern generation for analog integrated circuits. [Citation Graph (0, 0)][DBLP]
   VTS, 1997, pp:296-301 [Conf]
   
9. Mustafa Badaroglu, Kris Tiri, Geert Van der Plas, Piet Wambacq, Ingrid Verbauwhede, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
   Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:1146-1154 [Journal]
   
10. Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
    Digital ground bounce reduction by supply current shaping and clock frequency Modulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:1, pp:65-76 [Journal]
    
11. Geert Van der Plas, Geert Debyser, Francky Leyn, Koen Lampaert, Jan Vandenbussche, Georges G. E. Gielen, Willy M. C. Sansen, Petar Veselinovic, Domine Leenaerts
    AMGIE-A synthesis environment for CMOS analog integrated circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:9, pp:1037-1058 [Journal]
    
12. Geert Van der Plas, Jan Vandenbussche, Georges G. E. Gielen, Willy M. C. Sansen
    A layout synthesis methodology for array-type analog blocks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:6, pp:645-661 [Journal]
    
13. Carl De Ranter, Geert Van der Plas, Michiel Steyaert, Georges G. E. Gielen, Willy M. C. Sansen
    CYCLONE: automated design and layout of RF LC-oscillators. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:10, pp:1161-1170 [Journal]
    
14. Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
    SWAN: high-level simulation methodology for digital substrate noise generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:1, pp:23-33 [Journal]
    
15. Stephane Bronckers, Charlotte Soens, Geert Van der Plas, Gerd Vandersteen, Yves Rolain
    Interactive presentation: Simulation methodology and experimental verification for the analysis of substrate noise on LC-VCO's. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1520-1525 [Conf]
    
16. Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
    Scalable Gate-Level Models for Power and Timing Analysis. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2938-2941 [Conf]
    
17. Charlotte Soens, Geert Van der Plas, Piet Wambacq, Stéphane Donnay
    Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
    
18. 
    Mixed-Signal Design Space Exploration of Time-Interleaved A/D Converters for Ultra-Wide Band Applications. [Citation Graph (, )][DBLP]
    
    
19. 
    Evaluation of energy-recovering interconnects for low-power 3D stacked ICs. [Citation Graph (, )][DBLP]
    
    
20. 
    Automated Pathfinding tool chain for 3D-stacked integrated circuits: Practical case study. [Citation Graph (, )][DBLP]