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Vinod Narayanan:
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- Vinod Narayanan, Vijay Pitchumani
A Massively Parallel Algorithm for Fault Simulation on the Connection Machine. [Citation Graph (0, 0)][DBLP] DAC, 1989, pp:734-737 [Conf]
- Vinod Narayanan, Barbara A. Chappell, Bruce M. Fleischer
Static timing analysis for self resetting circuits. [Citation Graph (0, 0)][DBLP] ICCAD, 1996, pp:119-126 [Conf]
- Kenneth L. Shepard, Vinod Narayanan
Noise in deep submicron digital design. [Citation Graph (0, 0)][DBLP] ICCAD, 1996, pp:524-531 [Conf]
- Kenneth L. Shepard, Vinod Narayanan, Peter C. Elmendorf, Gutuan Zheng
Global harmony: coupled noise analysis for full-chip RC interconnect networks. [Citation Graph (0, 0)][DBLP] ICCAD, 1997, pp:139-146 [Conf]
- Vinod Narayanan, Vijay Pitchumani
: A Parallel Algorithm for Fault Simulation on the Connection Machine. [Citation Graph (0, 0)][DBLP] ITC, 1988, pp:89-93 [Conf]
- Kenneth L. Shepard, Vinod Narayanan
Conquering Noise in Deep-Submicron Digital ICs. [Citation Graph (0, 0)][DBLP] IEEE Design & Test of Computers, 1998, v:15, n:1, pp:51-62 [Journal]
- Kenneth L. Shepard, Vinod Narayanan, Ron Rose
Harmony: static noise analysis of deep submicron digital integrated circuits. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:8, pp:1132-1150 [Journal]
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