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Yoichi Shiraishi: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yasushi Ogawa, Tatsuki Ishii, Yoichi Shiraishi, Hidekazu Terai, Tokinori Kozawa, Kyoji Yuyama, Kyoji Chiba
    Efficient placement algorithms optimizing delay for high-speed ECL masterslice LSIs. [Citation Graph (0, 0)][DBLP]
    DAC, 1986, pp:404-410 [Conf]
  2. Yoichi Shiraishi, Jun'ya Sakemi, Makoto Kutsuwada, Akira Tsukizoe, Takashi Satoh
    A High Packing Density Module Generator for CMOS Logic Cells. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:439-444 [Conf]
  3. Yoichi Shiraishi, Mitsuyuki Kimura, Kazuhiko Kobayashi, Tetsuro Hino, Miki Seriuchi, Manabu Kusaoke
    A High-Packing Density Module Generator for Bipolar Analog LSIs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:194-197 [Conf]
  4. Jie Zhou, Yoichi Shiraishi, Ushio Yamamoto, Yoshikuni Onozato
    Dynamic Allocation of Transmitter Power in a DS-CDMA Cellular System Using Genetic Algorithms. [Citation Graph (0, 0)][DBLP]
    ICN (1), 2001, pp:579-588 [Conf]
  5. Yoichi Shiraishi, Jun'ya Sakemi
    A Permeation Router. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:3, pp:462-471 [Journal]
  6. Yoichi Shiraishi, Jun'ya Sakemi, Kazuyuki Fukuda
    Optimality of a feedthrough assignment algorithm in a CMOS logic cell layout. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:8, pp:982-993 [Journal]

  7. Solution Space Reduction of Simulated Evolution Algorithm for Solving Standard Cell Placement Problem. [Citation Graph (, )][DBLP]


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