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Jeffrey E. Nelson: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jeffrey E. Nelson, Jason G. Brown, Rao Desineni, R. D. (Shawn) Blanton
    Multiple-detect ATPG based on physical neighborhoods. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:1099-1102 [Conf]
  2. JoAnn M. Paul, Alex Bobrek, Jeffrey E. Nelson, Joshua J. Pieper, Donald E. Thomas
    Schedulers as model-based design elements in programmable heterogeneous multiprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:408-411 [Conf]
  3. Alex Bobrek, Joshua J. Pieper, Jeffrey E. Nelson, JoAnn M. Paul, Donald E. Thomas
    Modeling Shared Resource Contention Using a Hybrid Simulation/Analytical Approach. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1144-1149 [Conf]
  4. Jeffrey E. Nelson, Thomas Zanon, Rao Desineni, Jason G. Brown, N. Patil, Wojciech Maly, R. D. (Shawn) Blanton
    Extraction of defect density and size distributions from wafer sort test results. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:913-918 [Conf]
  5. Thomas J. Vogels, Thomas Zanon, Rao Desineni, R. D. (Shawn) Blanton, Wojciech Maly, Jason G. Brown, Jeffrey E. Nelson, Y. Fei, X. Huang, Padmini Gopalakrishnan, Mahim Mishra, V. Rovner, S. Tiwary
    Benchmarking Diagnosis Algorithms With a Diverse Set of IC Deformations. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:508-517 [Conf]
  6. Jeffrey E. Nelson, Thomas Zanon, Jason G. Brown, Osei Poku, R. D. (Shawn) Blanton, Wojciech Maly, Brady Benware, Chris Schuermyer
    Extracting Defect Density and Size Distributions from Product ICs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2006, v:23, n:5, pp:390-400 [Journal]
  7. Ronald F. Brender, Jeffrey E. Nelson, Mark E. Arsenault
    Debugging Optimized Code: Concepts and Implementation on DIGITAL Alpha Systems. [Citation Graph (0, 0)][DBLP]
    Digital Technical Journal, 1998, v:10, n:1, pp:81-99 [Journal]
  8. Brett H. Meyer, Joshua J. Pieper, JoAnn M. Paul, Jeffrey E. Nelson, Sean M. Pieper, Anthony G. Rowe
    Power-Performance Simulation and Design Strategies for Single-Chip Heterogeneous Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:6, pp:684-697 [Journal]

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