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R. D. (Shawn) Blanton: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jeffrey E. Nelson, Jason G. Brown, Rao Desineni, R. D. (Shawn) Blanton
    Multiple-detect ATPG based on physical neighborhoods. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:1099-1102 [Conf]
  2. Sounil Biswas, Peng Li, R. D. (Shawn) Blanton, Larry T. Pileggi
    Specification Test Compaction for Analog Circuits and MEMS. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:164-169 [Conf]
  3. Jeffrey E. Nelson, Thomas Zanon, Rao Desineni, Jason G. Brown, N. Patil, Wojciech Maly, R. D. (Shawn) Blanton
    Extraction of defect density and size distributions from wafer sort test results. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:913-918 [Conf]
  4. Rahul Kundu, R. D. (Shawn) Blanton
    ATPG for Noise-Induced Switch Failures in Domino Logic. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:765-769 [Conf]
  5. R. D. (Shawn) Blanton, Kumar N. Dwarakanath, Anirudh B. Shah
    Analyzing the Effectiveness of Multiple-Detect Test Sets. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:876-885 [Conf]
  6. Jason G. Brown, R. D. (Shawn) Blanton
    CAEN-BIST: Testing the NanoFabric. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:462-471 [Conf]
  7. Nilmoni Deb, R. D. (Shawn) Blanton
    Built-In Self Test of CMOS-MEMS Accelerometers. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1075-1084 [Conf]
  8. Rahul Kundu, R. D. (Shawn) Blanton
    Path Delay Test Generation for Domino Logic Circuits in the Presence of Crosstalk. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:122-130 [Conf]
  9. Wojciech Maly, Anne E. Gattiker, Thomas Zanon, Thomas J. Vogels, R. D. (Shawn) Blanton, Thomas M. Storey
    Deformations of IC Structure in Test and Yield Learning. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:856-865 [Conf]
  10. Thomas J. Vogels, Wojciech Maly, R. D. (Shawn) Blanton
    Progressive Bridge Identification. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:309-318 [Conf]
  11. Thomas J. Vogels, Thomas Zanon, Rao Desineni, R. D. (Shawn) Blanton, Wojciech Maly, Jason G. Brown, Jeffrey E. Nelson, Y. Fei, X. Huang, Padmini Gopalakrishnan, Mahim Mishra, V. Rovner, S. Tiwary
    Benchmarking Diagnosis Algorithms With a Diverse Set of IC Deformations. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:508-517 [Conf]
  12. R. D. (Shawn) Blanton
    IDDQ-Testability of Tree Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:78-86 [Conf]
  13. R. D. (Shawn) Blanton, Subhasish Mitra
    Testing Nanometer Digital Integration Circuits: Myths, Reality and the Road Ahead. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:8-9 [Conf]
  14. Noppanunt Utamaphethai, R. D. (Shawn) Blanton, John Paul Shen
    Superscalar Processor Validation at the Microarchitecture Level. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:300-305 [Conf]
  15. Sounil Biswas, Kumar N. Dwarakanath, R. D. (Shawn) Blanton
    Generalized Sensitization using Fault Tuples. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:297-303 [Conf]
  16. R. D. (Shawn) Blanton, John P. Hayes
    Design of a fast, easily testable ALU. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:9-16 [Conf]
  17. Jason G. Brown, R. D. (Shawn) Blanton
    Exploiting Regularity for Inductive Fault Analysis. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:364-369 [Conf]
  18. Kumar N. Dwarakanath, R. D. (Shawn) Blanton
    Exploiting Dominance and Equivalence using Fault Tuples. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:269-274 [Conf]
  19. Nilmoni Deb, R. D. (Shawn) Blanton
    Multi-Modal Built-In Self-Test for Symmetric Microsystems. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:139-147 [Conf]
  20. Rao Desineni, R. D. (Shawn) Blanton
    Diagnosis of Arbitrary Defects Using Neighborhood Function Extraction. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:366-373 [Conf]
  21. Keerthi Heragu, Manish Sharma, Rahul Kundu, R. D. (Shawn) Blanton
    Testing of Dynamic Logic Circuits Based on Charge Sharing. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:396-403 [Conf]
  22. Rahul Kundu, R. D. (Shawn) Blanton
    Timed Test Generation Crosstalk Switch Failures in Domino CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:379-388 [Conf]
  23. Salvador Mir, H. Bederr, R. D. (Shawn) Blanton, Hans G. Kerkhoff, H. J. Klim
    SoCs with MEMS? Can We Include MEMS in the SoCs Design and Test Flow? [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:449-450 [Conf]
  24. Bernard Courtois, R. D. (Shawn) Blanton
    Guest Editors' Introduction. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1999, v:16, n:4, pp:16-17 [Journal]
  25. Tamal Mukherjee, Gary K. Fedder, R. D. (Shawn) Blanton
    Hierarchical Design and Test of Integrated Microsystems. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1999, v:16, n:4, pp:18-27 [Journal]
  26. Jeffrey E. Nelson, Thomas Zanon, Jason G. Brown, Osei Poku, R. D. (Shawn) Blanton, Wojciech Maly, Brady Benware, Chris Schuermyer
    Extracting Defect Density and Size Distributions from Product ICs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2006, v:23, n:5, pp:390-400 [Journal]
  27. Noppanunt Utamaphethai, R. D. (Shawn) Blanton, John Paul Shen
    Effectiveness of Microarchitecture Test Program Generation. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:4, pp:38-49 [Journal]
  28. Tao Jiang, R. D. (Shawn) Blanton
    Inductive fault analysis of surface-micromachined MEMS. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:1104-1116 [Journal]
  29. Sounil Biswas, Peng Li, R. D. (Shawn) Blanton, Larry T. Pileggi
    Specification Test Compaction for Analog Circuits and MEMS [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  30. Jason G. Brown, R. D. (Shawn) Blanton
    A Built-in Self-test and Diagnosis Strategy for Chemically Assembled Electronic Nanotechnology. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2007, v:23, n:2-3, pp:131-144 [Journal]

  31. Precise failure localization using automated layout analysis of diagnosis candidates. [Citation Graph (, )][DBLP]


  32. Multiple defect diagnosis using no assumptions on failing pattern characteristics. [Citation Graph (, )][DBLP]


  33. Automated failure population creation for validating integrated circuit diagnosis methods. [Citation Graph (, )][DBLP]


  34. Virtual probe: A statistically optimal framework for minimum-cost silicon characterization of nanoscale integrated circuits. [Citation Graph (, )][DBLP]


  35. Automated Standard Cell Library Analysis for Improved Defect Modeling. [Citation Graph (, )][DBLP]


  36. Test Compaction for Mixed-Signal Circuits Using Pass-Fail Test Data. [Citation Graph (, )][DBLP]


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