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Kundan Nepal: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky
    Designing logic circuits for probabilistic computation in the presence of noise. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:485-490 [Conf]
  2. Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky
    Designing MRF based error correcting circuits for memory elements. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:792-793 [Conf]
  3. Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky
    Optimizing noise-immune nanoscale circuits using principles of Markov random fields. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:149-152 [Conf]
  4. Kundan Nepal, Hui-Yuan Song, R. Iris Bahar, Joel Grodstein
    RESTA: a robust and extendable symbolic timing analysis tool. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:407-412 [Conf]
  5. Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky
    MRF Reinforcer: A Probabilistic Element for Space Redundancy in Nanoscale Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2006, v:26, n:5, pp:19-27 [Journal]
  6. R. Iris Bahar, Hui-Yuan Song, Kundan Nepal, Joel Grodstein
    Symbolic failure analysis of complex CMOS circuits due to excessive leakage current and charge sharing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:4, pp:502-515 [Journal]
  7. Hui-Yuan Song, Kundan Nepal, R. Iris Bahar, Joel Grodstein
    Timing analysis for full-custom circuits using symbolic DC formulations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:9, pp:1815-1830 [Journal]
  8. Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky
    Interactive presentation: Techniques for designing noise-tolerant multi-level combinational circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:576-581 [Conf]
  9. Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky
    Designing Nanoscale Logic Circuits Based on Markov Random Fields. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2007, v:23, n:2-3, pp:255-266 [Journal]

  10. Detecting errors using multi-cycle invariance information. [Citation Graph (, )][DBLP]


  11. Improving the testability and reliability of sequential circuits with invariant logic. [Citation Graph (, )][DBLP]


  12. Compacting test vector sets via strategic use of implications. [Citation Graph (, )][DBLP]


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